Texas Instruments SN75LVDM976DGG, SN75LVDM976DGGR, SN75LVDM976DL, SN75LVDM976DLR, SN75LVDM977DGG Datasheet

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SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
9 Channels for the Data and Control Paths of the Small Computer Systems Interface (SCSI)
D
Supports Single-Ended and Low-Voltage Differential (LVD) SCSI
D
CMOS Input Levels (’LVDM976) or TTL Input Levels (’LVDM977) Available
D
Includes DIFFSENS Comparators on CDE0
D
Single-Ended Receivers Include Noise Pulse Rejection Circuitry
D
Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch
D
Low Disabled Supply Current 7 mA Maximum
D
Power-Up/Down Glitch Protection
D
Bus is High-Impedance With VCC = 1.5 V
D
Pin-Compatible With the SN75976ADGG High-Voltage Differential Transceiver
description
The SN75LVDM976 and SN75LVDM977 have nine transceivers for transmitting or receiving the signals to or from a SCSI data bus. They offer electrical compatibility to both the single-ended signaling of X3.277:1996–SCSI–3 Parallel Inter­face (Fast–20) and the new low-voltage differen­tial signaling method of proposed standard 1142–D SCSI Parallel Interface – 2 (SPI–2).
The differential drivers are nonsymmetrical. The SCSI bus uses a dc bias on the line to allow terminated fail safe and wired-OR signaling. This bias can be as high as 125 mV and induces a difference in the high-to-low and low-to-high transition times of a symmetrical driver. In order to reduce pulse skew, an LVD SCSI driver’s output characteristics become nonsymmetrical. In other words, there is more assertion current than negation current to or from the driver. This allows the actual differential signal voltage on the bus to be symmetrical about 0 V. Even though the driver output characteristics are nonsymmetrical, the design of the ’L VDM976 drivers maintains balanced signaling. Balanced means that the current that flows in each signal line is nearly equal but opposite in direction and is one of the keys to the low-noise performance of a differential bus.
AVAILABLE OPTIONS
PACKAGE
T
A
TSSOP
(DGG)
CMOS INPUT LEVELS
TSSOP
(DGG)
TTL INPUTS LEVELS
0°C to 70°C
SN75LVDM976DGG SN75LVDM976DGGR
SN75LVDM977DGG SN75LVDM977DGGR
The R suffix designates a taped and reeled package.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG PACKAGE
(TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
INV/NON
GND GND
1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
V
CC
GND GND GND GND GND
V
CC
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE
CDE2 CDE1 CDE0 9B+ 9B
8B+ 8B
7B+ 7B
6B+ 6B
V
CC
GND GND GND GND GND V
CC
5B+ 5B
4B+ 4B
3B+ 3B
2B+ 2B
1B+ 1B
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
The signal symmetry requirements of the L VD-SCSI bus mean you can no longer obtain logical inversion of a signal by simply reversing the differential signal connections. This requires the ability to invert the logic convention through the INV/NON terminal. This input would be a low for SCSI controllers with active-high data and high for active-low data. In either case, the B+ signals of the transceiver must be connected to the SIGNAL+ line of the SCSI bus and the B– of the transceiver to the SIGNAL– line.
The CDE0 input incorporates a window comparator to detect the status of the DIFFSENS line of a SCSI bus. This line is below 0.5 V, if using single-ended signals, between 1.7 V and 1.9 V if low-voltage differential, and between 2.4 V and 5.5 V if high-voltage differential. The outputs assume the characteristics of single-ended or L VD accordingly or place the outputs into high-impedance, when HVD is detected. This, and the INV/NON
input,
are the only differences to the trade-standard function of the SN75976A HVD transceiver. Two options are offered to minimize the signal noise margins on the interface between the communications
controller and the transceiver. The SN75LVDM976 has logic input voltage thresholds of about 0.5 VCC. The SN75L VDM977 has a fixed logic input voltage threshold of about 1.5 V. The input voltage threshold should be selected to be near the middle of the output voltage swing of the corresponding driver circuit.
The SN75L VDM976 and SN75L VDM977 are characterized for operation over an free-air temperature range of T
A
= 0°C to 70°C.
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
1B–
2B– 2B+ 3B– 3B+ 4B– 4B+
Channel 4
Channel 3
Channel 2
4DE/RE
4A
3DE/RE
3A
2DE/RE
2A
1DE/RE
1A
CDE1
CDE0
+ –
– +
1B+
INV/NON
5B– 5B+ 6B– 6B+ 7B– 7B+
Channel 7
Channel 6
Channel 5
7DE/RE
7A
6DE/RE
6A
5DE/RE
5A
8B– 8B+
Channel 8
8DE/RE
8A
2.4 V (Internal)
0.5 V (Internal)
CDE2
9B–
9DE/RE
9A
9B+
1DEb 1DEa
1REb 1REa
SE
LVD
SE LVD
SE LVDINV/NON
INV/NON
9DEb 9DEa
9REb 9REa
1DEb
1REb
1DEa
1REa
9DEb
9REb
9DEa
9REa
A
B
B–
B+
A
DE/RE
V
ID
Figure 1. Inverting LVD Transceiver
B–
B+
A
DE/RE
Figure 2. Inverting Single-Ended Transceiver
B–
B+
A
Figure 3. Inverting Single-Ended Driver
B–
B+
A
Figure 4. Inverting LVD Driver
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagrams and function tables
FUNCTION TABLE
Inputs
Outputs
(B+ – B–) DE/RE A B+ B– A
VID 30 mV L NA Z Z L
–30 mV < VID < 30 mV L NA Z Z ?
VID –30 mV L NA Z Z H Open circuit L NA Z Z ?
NA H L H L Z NA H H L H Z
FUNCTION TABLE
Inputs
Outputs
B– DE/RE A B+ B– A
H L NA L Z L L L NA L Z H
Open circuit L NA L Z ?
NA H L L H Z NA H H L L Z
FUNCTION TABLE
Input
Outputs
A B+ B–
L L H H L L
FUNCTION TABLE
Input
Outputs
A B+ B–
L H L H L H
B–
B+
A
Figure 5. Noninverting LVD Driver
B–
B+
A
DE/RE
V
ID
Figure 6. Noninverting LVD Transceiver
B–
B+
A
DE/RE
Figure 7. Noninverting Single-Ended Transceiver
B–
B+
A
Figure 8. Noninverting Single-Ended Driver
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagrams and function tables (continued)
FUNCTION TABLE
Input
Outputs
A B+ B–
L L H H H L
FUNCTION TABLE
Inputs
Outputs
(B+ – B–) DE/RE A B+ B– A
VID 30 mV L NA Z Z H
–30 mV < VID < 30 mV L NA Z Z ?
VID –30 mV L NA Z Z L
Open circuit L NA Z Z ?
NA H L L H Z NA H H H L Z
FUNCTION TABLE
Inputs
Outputs
B– DE/RE A B+ B– A
H L NA L Z H L L NA L Z L
Open Circuit L NA L Z ?
NA H L L L Z NA H H L H Z
FUNCTION TABLE
Input
Outputs
A B+ B–
L L L H L H
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1B– 1B+
1A
1DE/RE
2B– 2B+
2A
2DE/RE
3B– 3B+
3A
3DE/RE
4B– 4B+
4A
4DE/RE
5B– 5B+
5A
5DE/RE
6B– 6B+
6A
6DE/RE
7B– 7B+
7A
7DE/RE
8B– 8B+
8A
8DE/RE
9B– 9B+
9A
9DE/RE
Control Inputs
CDE0 0.7 V < VI < 1.9 V
INV/NON
L CDE1 L CDE2 L
(a)
1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
5A
6A
7A
8A
9A
9DE/RE
Control Inputs
CDE0 0.7 V < VI < 1.9 V
INV/NON
L CDE1 L CDE2 H
1B– 1B+
2B– 2B+
3B– 3B+
4B– 4B+
5B– 5B+
6B– 6B+
7B– 7B+
8B– 8B+
9B– 9B+
(b)
1A
2A
3A
4A
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE
Control Inputs
CDE0 0.7 V < VI < 1.9 V
INV/NON
L CDE1 H CDE2 L
1B– 1B+
2B– 2B+
3B– 3B+
4B– 4B+
5B– 5B+
6B– 6B+
7B– 7B+
8B– 8B+
9B– 9B+
(c)
Figure 9. Logic Diagrams
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1A
2A
3A
4A
5A
6A
7A
8A
9A
9DE/RE
1B– 1B+
2B– 2B+
3B– 3B+
4B– 4B+
5B– 5B+
6B– 6B+
7B– 7B+
8B– 8B+
9B– 9B+
Control Inputs
CDE0 0.7 V < VI < 1.9 V
INV/NON
L CDE1 H CDE2 H
(a)
1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE
1B– 1B+
2B– 2B+
3B– 3B+
4B– 4B+
5B– 5B+
6B– 6B+
7B– 7B+
8B– 8B+
9B– 9B+
Control Inputs
CDE0 0.7 V < VI < 1.9 V
INV/NON
H CDE1 L CDE2 L
(b)
1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
5A
6A
7A
8A
9A
9DE/RE
Control Inputs
CDE0 0.7 V < VI < 1.9 V
INV/NON
H CDE1 L CDE2 H
(C)
1B– 1B+
2B– 2B+
3B– 3B+
4B– 4B+
5B– 5B+
6B– 6B+
7B– 7B+
8B– 8B+
9B– 9B+
Figure 10. Logic Diagrams
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1A
2A
3A
4A
5A
6A
7A
8A
9A
9DE/RE
1B– 1B+
2B– 2B+
3B– 3B+
4B– 4B+
5B– 5B+
6B– 6B+
7B– 7B+
8B– 8B+
9B– 9B+
Control Inputs
CDE0 0.7 V < VI < 1.9 V
INV/NON
H CDE1 H CDE2 H
(a)
1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE
1B–
1B+ 2B–
2B+ 3B–
3B+ 4B–
4B+ 5B–
5B+ 6B–
6B+
7B–
7B+ 8B–
8B+ 9B–
9B+
Control Inputs
CDE0 VI < 0.5 V
INV/NON
L CDE1 L CDE2 L
(b)
1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
5A
6A
7A
8A
9A
9DE/RE
1B–
1B+ 2B–
2B+ 3B–
3B+ 4B–
4B+ 5B–
5B+
6B–
6B+
7B–
7B+
8B–
8B+
9B–
9B+
Control Inputs
CDE0 VI < 0.5 V
INV/NON
L CDE1 L CDE2 H
(c)
Figure 11. Logic Diagrams
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1A
2A
3A
4A
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE
1B–
1B+
2B–
2B+
3B–
3B+
4B–
4B+
5B–
5B+ 6B–
6B+
7B–
7B+ 8B–
8B+ 9B–
9B+
Control Inputs
CDE0 VI < 0.5 V
INV/NON
L CDE1 H CDE2 L
(a)
Control Inputs
CDE0 VI < 0.5 V
INV/NON
L CDE1 H CDE2 H
(b)
1A
2A
3A
4A
5A
6A
7A
8A
9A
9DE/RE
1B–
1B+
2B–
2B+
3B–
3B+
4B–
4B+
5B–
5B+
6B–
6B+
7B–
7B+
8B–
8B+
9B–
9B+
Control Inputs
CDE0 VI < 0.5 V
INV/NON
H CDE1 L CDE2 L
(c)
1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE
1B–
1B+ 2B–
2B+ 3B–
3B+ 4B–
4B+ 5B–
5B+ 6B–
6B+
7B–
7B+ 8B–
8B+ 9B–
9B+
Figure 12. Logic Diagrams
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