SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
9 Channels for the Data and Control Paths
of the Small Computer Systems Interface
(SCSI)
D
Supports Single-Ended and Low-Voltage
Differential (LVD) SCSI
D
CMOS Input Levels (’LVDM976) or TTL
Input Levels (’LVDM977) Available
D
Includes DIFFSENS Comparators on CDE0
D
Single-Ended Receivers Include Noise
Pulse Rejection Circuitry
D
Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
D
Low Disabled Supply Current 7 mA
Maximum
D
Power-Up/Down Glitch Protection
D
Bus is High-Impedance With VCC = 1.5 V
D
Pin-Compatible With the SN75976ADGG
High-Voltage Differential Transceiver
description
The SN75LVDM976 and SN75LVDM977 have
nine transceivers for transmitting or receiving the
signals to or from a SCSI data bus. They offer
electrical compatibility to both the single-ended
signaling of X3.277:1996–SCSI–3 Parallel Interface (Fast–20) and the new low-voltage differential signaling method of proposed standard
1142–D SCSI Parallel Interface – 2 (SPI–2).
The differential drivers are nonsymmetrical. The
SCSI bus uses a dc bias on the line to allow
terminated fail safe and wired-OR signaling. This bias can be as high as 125 mV and induces a difference in
the high-to-low and low-to-high transition times of a symmetrical driver. In order to reduce pulse skew, an LVD
SCSI driver’s output characteristics become nonsymmetrical. In other words, there is more assertion current
than negation current to or from the driver. This allows the actual differential signal voltage on the bus to be
symmetrical about 0 V. Even though the driver output characteristics are nonsymmetrical, the design of the
’L VDM976 drivers maintains balanced signaling. Balanced means that the current that flows in each signal line
is nearly equal but opposite in direction and is one of the keys to the low-noise performance of a differential bus.
AVAILABLE OPTIONS
PACKAGE
T
A
TSSOP
(DGG)
CMOS INPUT LEVELS
TSSOP
(DGG)
TTL INPUTS LEVELS
0°C to 70°C
SN75LVDM976DGG
SN75LVDM976DGGR
†
SN75LVDM977DGG
SN75LVDM977DGGR
†
†
The R suffix designates a taped and reeled package.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
INV/NON
GND
GND
1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
V
CC
GND
GND
GND
GND
GND
V
CC
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE
CDE2
CDE1
CDE0
9B+
9B
–
8B+
8B
–
7B+
7B
–
6B+
6B
–
V
CC
GND
GND
GND
GND
GND
V
CC
5B+
5B
–
4B+
4B
–
3B+
3B
–
2B+
2B
–
1B+
1B
–