•Integrated Output Squelch•High Protection Against ESD Transient
•Programmable Rx/Tx Equalization and– HBM: 10,000 V
De-Emphasis Width Control
•Power-Save Feature Lowers Power by >80% in
Auto Low-Power Mode
•Low Power
– <220 mW Typ.APPLICATIONS
– <50 mW (in Auto Low-Power Mode)
– <5m W (in Standby Mode)
•Excellent Jitter and Loss Compensation
Capability to Over 24-Inch (61-cm) FR4 Trace
DESCRIPTION
The SN75LVCP601 is a dual-channel, single-lane SATA redriver and signal conditioner supporting data rates up
to 6 Gbps. The device complies with SATA physical link 2m and 3i specifications. The SN75LVCP601 operates
from a single 3.3-V supply and has 100-Ω line termination with a self-biasing feature, making the device suitable
for ac coupling. The inputs incorporate an out-of-band (OOB) detector, which automatically squelches the output
while maintaining a stable common-mode voltage compliant to the SATA link. The device is also designed to
handle spread-spectrum clocking (SSC) transmission per the SATA specification.
The SN75LVCP601 handles interconnect losses at both its input and output. The input stage of each channel
offers selectable equalization settings that can be programmed to match the loss in the channel. The differential
outputs provide selectable de-emphasis to compensate for the distortion that the SATA signal is expected to
experience. The level of equalization and de-emphasis settings depends on the length of interconnect and its
characteristics. Both equalization and de-emphasis levels are controlled by the setting of signal control pins EQ1,
EQ2, DE1, and DE2.
The device is hot-plug capable (requires the use of ac-coupling capacitors at differential inputs and outputs),
preventing device damage under device hot-insertion, such as async signal plug/removal, unpowered
plug/removal, powered plug/removal, or surprise plug/removal.
(1) For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
7ENI, LVCMOSDevice enable/disable pin, internally pulled to VCC. See Table 2.
8, 9DE1, DE2
17, 19EQ1, EQ2
16, 6DEW1, DEW2I, LVCMOSDe-emphasis width control for CH 1 and CH 2. See Table 2.
POWER
10, 20VccPowerPositive supply should be 3.3 V ± 10%.
3, 13, 18GNDPowerSupply ground
(1) Internally biased to Vcc/2 with >200-kΩ pullup/pulldown. When 3-state pins are left as NC, board leakage at the pin pad must be <1 µA;
otherwise, drive to Vcc/2 to assert mid-level state.
(1)
(1)
PIN TYPEDESCRIPTION
Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins are
tied to an internal voltage bias by a dual-termination resistor circuit.
Non-inverting and inverting VML differential output for CH 1 and CH 2. These pins are
internally tied to voltage bias by termination resistors.
I, LVCMOSSelects de-emphasis settings for CH 1 and CH 2 per Table 1. Internally tied to VCC/2
I, LVCMOSSelects equalization settings for CH 1 and CH 2 per Table 1. Internally tied to VCC/2
output de-emphasis) to meet SATA loss and jitter spec.
Actual trace length supported by the LVCP601 may be more or less than suggested values and depends on board
layout, trace widths, and number of connectors used in the SATA signal path.
Figure 3. Trace Length Example* for LVCP601
15
14
13
12
11
1
2
3
4
5
3.3 V
LVCP601 RTJ
RX1P
RX1N
TX2N
TX2P
TX1P
TX1N
RX2N
RX2P
10 nF
10 nF
10 nF
10 nF
10 nF
10 nF
10 nF
10 nF
EQ2
EQ1
DEW1
20
19
18
17
16
6
7
8
9
10
1.0 Fm
1.0 Fm
1.0 Fm
SATA Host
SATA
Connector
DEW2
EN
DE1
DE2
Vcc
Vcc
SN75LVCP601
SLLSE41B –JUNE 2010– REVISED FEBRUARY 2012
(1) Place supply capacitors close to device pin.
(2) EN can be left open or tied to supply when no external control is implemented.
(3) Output de-emphasis selection is set at –2 dB, EQ at 7 dB, and DE duration for SATA I/II/III operation for both
channels.
(4) Actual EQ/DE duration settings depend on device placement relative to host and SATA connector.
Figure 4. Typical Device Implementation
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OPERATION DESCRIPTION
INPUT EQUALIZATION
Each differential input of the SN75LVCP601 has programmable equalization in its front stage. The equalization
setting is shown in Table 1. The input equalizer is designed to recover a signal even when no eye is present at
the receiver, and effectively supports FR4 trace at the input anywhere from 4 in. (10.2 cm) to 20 in. (50.8 cm) at
SATA 6G speed.
OUTPUT DE-EMPHASIS
The SN75LVCP601 provides the de-emphasis settings shown in Table 1. De-emphasis is controlled
independently for each channel, and is set by the control pins DE1 and DE2 as shown in Table 1. There are two
de-emphasis duration settings available in the device. DEW1 and DEW2 control the DE durations for channels
one and two, respectively. The recommended settings for these control pins are listed Table 1. Output
de-emphasis is capable of supporting FR4 trace at the output anywhere from 2 in. (5.1 cm) to 12 in. (30.5 cm) at
SATA 3G/6G speed.
LOW-POWER MODE
Two low-power modes are supported by the SN75LVCP601, listed as follows:
1. Standby mode (triggered by the EN pin, EN = 0 V)
– Low-power mode is controlled by the enable (EN) pin. In its default state, this pin is internally pulled high.
Pulling this pin LOW puts the device in standby mode within 2 µs (max). In this mode, all active
components of the device are driven to their quiescent level, and differential outputs are driven to Hi-Z
(open). Maximum power dissipation in this mode is 5 mW. Exiting from this mode to normal operation
requires a maximum latency of 5 µs.
2. Auto low-power mode (triggered when a given channel is in the electrically idle state for more than 100 µs
and EN = Vcc)
– The device enters and exits low-power mode by actively monitoring the input signal (VIDp-p) level on
each of its channels independently. When the input signal on either or both channels is in the electrically
idle state, that is, VIDp-p < 50 mV and stays in this state for >100 µs, the associated channel(s) enters
into the low-power state. In this state, output of the associated channel(s) is driven to VCM and the
device selectively shuts off some circuitry to lower power by >80% of its normal operating power. Exit
time from the auto low-power mode is <50 ns.
Out-of-Band (OOB) SUPPORT
The squelch detector circuit within the device enables full detection of OOB signaling as specified in the SATA
specification. Differential signal amplitude at the receiver input of 50 mVpp or less is not detected as an activity
and hence not passed to the output. Differential signal amplitude of 150 mVp-p or more is detected as an activity
and therefore passed to the output, indicating activity. Squelch circuit ON/OFF time is 5 ns, maximum. While in
squelch mode, outputs are held to VCM.
DEVICE POWER
The SN75LVCP601 is designed to operate from a single 3.3 V supply. Always practice proper power-supply
sequencing procedure. Apply Vcc first, before any input signals are applied to the device. The power-down
sequence is in reverse order.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage range
Voltage rangeDifferential I/O–0.5 to 4V
Electrostatic dischargeCharged-device model
Continuous power dissipationSee Thermal Table
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101-A.
(5) Tested in accordance with JEDEC Standard 22, Test Method A115-A.
(2)
V
CC
Control I/O–0.5 to Vcc + 0.5V
Human-body model
Machine model
(3)
(4)
(5)
(1)
VALUEUNIT
–0.5 to 4V
±10,000V
±1500V
±200V
THERMAL INFORMATION
SN75LVCP601
THERMAL METRIC
θ
JA
θ
JCtop
θ
JB
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
Device power dissipation in active mode215 to 288mW
Device power dissipation under standby mode5mW
(5)
(6)
(7)
0.5°C/W
0.9°C/W
15.2°C/W
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
(Typical values for all parameters are at VCC= 3.3V and TA= 25°C. All temp limits are specified by design)
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DEVICE PARAMETERS
P
D
P
SD
I
CC
I
CC_ALP
I
CC_STDBY
t
PDelay
AutoLP
AutoLP
t
ENB
t
DIS
ENTRY
EXIT
Power dissipation in active mode215288mW
Power dissipation in standbyEN = 0 V, DEWx = EQx = DEx = NC, K28.5
modepattern at 6 Gbps, VID= 700 mV
Active-mode supply current6580mA
Acive power-save mode I
CC
Standby mode supply currentEN = 0 V1mA
Maximum data rate16Gbps
Propagation delayMeasured using K28.5 pattern. See Figure 8.323400ps
Auto low-power entry timeElectrical idle at input; see Figure 9.80105130µs
Auto low-power exit timeAfter first signal activity; see Figure 9.4250ns
Device enable timeEN 0→15µs
Device disable timeEN 1→02µs
DEWx = EN = Vcc, EQx = DEx = NC, K28.5
pattern at 6 Gbps, VID= 700 mV
EN = 3.3 V, DEWx= 0 V, EQx/DEx = NC,
K28.5 pattern at 6 Gbps, VID= 700 mV
When device is enabled and auto low-power
conditions are met
Residual DJ 3Gbps
Residual DJ 6Gbps
Eye Opening 3Gbps
Eye Opening 6Gbps
SN75LVCP601
SLLSE41B –JUNE 2010– REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS (continued)
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RESIDUAL DJ AND EYE OPENING
vs
OUTPUT TRACE LENGTH
Figure 16.
SPACER
REVISION HISTORY
Changes from Revision A (October 2011) to Revision BPage
•Changed pin type from CML to VML for pins 4, 5, 14, 15 .................................................................................................... 4
Changes from Original (June 2010) to Revision APage
•Changed pin EN number From: 4 To: 7 ............................................................................................................................... 4
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
& no Sb/Br)
& no Sb/Br)
Lead/Ball Finish
(6)
CU NIPDAU | Call TILevel-2-260C-1 YEAR0 to 85LVC601
CU NIPDAU | Call TILevel-2-260C-1 YEAR0 to 85LVC601
MSL Peak Temp
(3)
Op Temp (°C)Device Marking
(4/5)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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