Texas Instruments SN75LVCP601RTJR Schematic [ru]
SN75LVCP601
www.ti.com
SLLSE41B –JUNE 2010– REVISED FEBRUARY 2012
Two-Channel SATA 6-Gb/s Redriver
Check for Samples: SN75LVCP601
1
FEATURES
• 1.5/3/6-Gbps Two-Channel Redriver • 20-Pin 4-mm × 4-mm QFN Package
• Integrated Output Squelch • High Protection Against ESD Transient
• Programmable Rx/Tx Equalization and – HBM: 10,000 V
De-Emphasis Width Control
• Power-Save Feature Lowers Power by >80% in
Auto Low-Power Mode
• Low Power – <220 mW Typ. APPLICATIONS – <50 mW (in Auto Low-Power Mode) – <5m W (in Standby Mode)
• Excellent Jitter and Loss Compensation
Capability to Over 24-Inch (61-cm) FR4 Trace
DESCRIPTION
The SN75LVCP601 is a dual-channel, single-lane SATA redriver and signal conditioner supporting data rates up
to 6 Gbps. The device complies with SATA physical link 2m and 3i specifications. The SN75LVCP601 operates
from a single 3.3-V supply and has 100-Ω line termination with a self-biasing feature, making the device suitable
for ac coupling. The inputs incorporate an out-of-band (OOB) detector, which automatically squelches the output
while maintaining a stable common-mode voltage compliant to the SATA link. The device is also designed to
handle spread-spectrum clocking (SSC) transmission per the SATA specification.
The SN75LVCP601 handles interconnect losses at both its input and output. The input stage of each channel
offers selectable equalization settings that can be programmed to match the loss in the channel. The differential
outputs provide selectable de-emphasis to compensate for the distortion that the SATA signal is expected to
experience. The level of equalization and de-emphasis settings depends on the length of interconnect and its
characteristics. Both equalization and de-emphasis levels are controlled by the setting of signal control pins EQ1,
EQ2, DE1, and DE2.
The device is hot-plug capable (requires the use of ac-coupling capacitors at differential inputs and outputs),
preventing device damage under device hot-insertion, such as async signal plug/removal, unpowered
plug/removal, powered plug/removal, or surprise plug/removal.
– CDM: 1,500 V
– MM: 200 V
• Pin-Compatible to LVCP412A/MAX4951
• Notebooks, Desktops, Docking Stations,
Servers, and Workstations
ORDERING INFORMATION
PART NUMBER PART MARKING PACKAGE
SN75LVCP601RTJR LVC601 20-pin RTJ, reel (large)
SN75LVCP601RTJT LVC601 20-pin RTJ, reel (small)
(1) For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
(1)
Copyright © 2010–2012, Texas Instruments Incorporated
ICH
R
HDD
eSATA
Cable
eSATA
connector
PC/WSMB
R = SN75LVCP601
ICH
R
Notebook
Dock
Dock Connector
PC/Workstation
Motherboard
NotebookDock
HDD
eSATA Cable
(2m)
eSATA
connector
SATA 6GHost
HDD
DTMB
DesktopMainBoard
iSATA
connector
R
SN75LVCP601
SLLSE41B –JUNE 2010– REVISED FEBRUARY 2012
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
www.ti.com
Figure 1. Typical Application
2 Copyright © 2010–2012, Texas Instruments Incorporated
RX1P [1]
CTRL
RT
RT
VBB= 1.7 V TYP
V
BB
RT
RT
Equalizer
Equalizer
Driver
Driver
OOB
Detect
OOB
Detect
SN75LVCP601
TX1P [15]
RX1N [2]
TX1N [14]
RX2N [12]
RX2P [11]
TX2N [4]
TX2P [5]
EN[7]
DE2[8]
DE1[9]
VCC[10,20]
GND[3,13,18]
EQ1[17]
EQ2[19]
DEW1 [16]
DEW2 [6]
SN75LVCP601
www.ti.com
SLLSE41B –JUNE 2010– REVISED FEBRUARY 2012
Figure 2. Data Flow Block Diagram
NAME PIN DESCRIPTION NAME PIN DESCRIPTION
RX1P 1 Input 1, non-inverting RX2P 11 Input 2, non-inverting
RX1N 2 Input 1, inverting RX2N 12 Input 2, inverting
GND 3 Ground GND 13 Ground
TX2N 4 Output 2, inverting TX1N 14 Output 1, inverting
TX2P 5 Output 2, non-inverting TX1P 15 Output 1, non-inverting
(1)
DEW2
(1)
EN
(2)
DE2
(2)
DE1
Vcc 10 3.3-V supply Vcc 20 3.3-V supply
(1) DEW1/2, EN tied to Vcc via internal PU resistor
(2) DE1, DE2, EQ1, EQ2 are tied to Vcc/2 via internal resistor
6 De-emphasis width cntrl.-CH 2 DEW1
7 Enable EQ1
8 De-emphasis CH2 GND 18 Ground
9 De-emphasis CH1 EQ2
PIN TABLE
(1)
(2)
(2)
16 De-emphasis width cntrl.-CH 1
17 EQ control CH 1
19 EQ control CH 2
Copyright © 2010–2012, Texas Instruments Incorporated 3
20
19
18
17
16
6
7
8
9
10
15
14
13
12
11
1
2
3
4
5
RX1P
RX1N
GND
TX2 N
TX2 P
VCC
EN
DE 2
DE 1
DEW 2
RX2P
RX2N
GND
TX1 N
TX1 P
EQ 2
EQ 1
VCC
DEW 1
GND
LVCP601RTJ
Thermal Pad must
be soldered to PCB
GND plane for
efficient thermal
performance
Bottom View
1
1
1
2
1
RX1P
RX1N
GND
TX2 N
TX2 P
DEW 2
DE 1
DE 2
EN
VCC
RX2P
RX2N
GND
TX1 N
TX1 P
VCC
DEW 1
EQ 2
EQ 1
GND
LVCP601RTJ
Top View
18
19
20
10
9
8
7
6
1
2
3
4
5
16
17
11
12
13
14
15
SN75LVCP601
SLLSE41B –JUNE 2010– REVISED FEBRUARY 2012
www.ti.com
PACKAGE PINOUT
PIN FUNCTIONS
PIN
NO. NAME
HIGH-SPEED DIFFERENTIAL I/O
2 RX1N I, CML
1 RX1P I, CML
12 RX2N I, CML
11 RX2P I, CML
14 TX1N O, VML
15 TX1P O, VML
4 TX2N O, VML
5 TX2P O, VML
CONTROL PINS
7 EN I, LVCMOS Device enable/disable pin, internally pulled to VCC. See Table 2.
8, 9 DE1, DE2
17, 19 EQ1, EQ2
16, 6 DEW1, DEW2 I, LVCMOS De-emphasis width control for CH 1 and CH 2. See Table 2.
POWER
10, 20 Vcc Power Positive supply should be 3.3 V ± 10%.
3, 13, 18 GND Power Supply ground
(1) Internally biased to Vcc/2 with >200-kΩ pullup/pulldown. When 3-state pins are left as NC, board leakage at the pin pad must be <1 µA;
otherwise, drive to Vcc/2 to assert mid-level state.
(1)
(1)
PIN TYPE DESCRIPTION
Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins are
tied to an internal voltage bias by a dual-termination resistor circuit.
Non-inverting and inverting VML differential output for CH 1 and CH 2. These pins are
internally tied to voltage bias by termination resistors.
I, LVCMOS Selects de-emphasis settings for CH 1 and CH 2 per Table 1. Internally tied to VCC/2
I, LVCMOS Selects equalization settings for CH 1 and CH 2 per Table 1. Internally tied to VCC/2
4 Copyright © 2010–2012, Texas Instruments Incorporated
16 in. (40.6 cm)
24 in. (61 cm)
SATA Host
Redriver
Redriver on Motherboard
Main Board
SATA Host
Redriver
Dock Board
Redriver on Dock Board
SATA
Connector
SATA
Connector
16 in. (40.6 cm)
8 in.
(20.3 cm)
8 in.
(20.3 cm)
24 in. (61 cm)
SN75LVCP601
www.ti.com
SLLSE41B –JUNE 2010– REVISED FEBRUARY 2012
Table 1. Tx/Rx EQ and DE Pulse-Duration Settings
DE1/DE2 EQ1/EQ2
NC (default) –4 NC (default) 0
0 0 0 7
1 –2 1 14
DEW1/DEW2 Device Function → DE Width for CH1/CH2
0 De-emphasis pulse duration, short (recommended setting when link operates at SATA
1 (default) De-emphasis pulse duration, long (recommended setting when link operates at SATA
CH1/CH2De-Emphasis CH1/CH2Equalization
dB (at 6Gbps) dB (at 6Gbps)
1.5/3/6 Gbps)
1.5/3 Gbps speed only)
Table 2. Control Pin Settings
EN Device Function → Standby Mode
0 Device in standby mode
1 (default) Device enabled
NOTE: *Trace lengths are suggested values based on TI spice simulations (done over programmable limits of input EQ and
Copyright © 2010–2012, Texas Instruments Incorporated 5
output de-emphasis) to meet SATA loss and jitter spec.
Actual trace length supported by the LVCP601 may be more or less than suggested values and depends on board
layout, trace widths, and number of connectors used in the SATA signal path.
Figure 3. Trace Length Example* for LVCP601
15
14
13
12
11
1
2
3
4
5
3.3 V
LVCP601 RTJ
RX1P
RX1N
TX2N
TX2P
TX1P
TX1N
RX2N
RX2P
10 nF
10 nF
10 nF
10 nF
10 nF
10 nF
10 nF
10 nF
EQ2
EQ1
DEW1
20
19
18
17
16
6
7
8
9
10
1.0 Fm
1.0 Fm
1.0 Fm
SATA Host
SATA
Connector
DEW2
EN
DE1
DE2
Vcc
Vcc
SN75LVCP601
SLLSE41B –JUNE 2010– REVISED FEBRUARY 2012
(1) Place supply capacitors close to device pin.
(2) EN can be left open or tied to supply when no external control is implemented.
(3) Output de-emphasis selection is set at –2 dB, EQ at 7 dB, and DE duration for SATA I/II/III operation for both
channels.
(4) Actual EQ/DE duration settings depend on device placement relative to host and SATA connector.
Figure 4. Typical Device Implementation
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OPERATION DESCRIPTION
INPUT EQUALIZATION
Each differential input of the SN75LVCP601 has programmable equalization in its front stage. The equalization
setting is shown in Table 1. The input equalizer is designed to recover a signal even when no eye is present at
the receiver, and effectively supports FR4 trace at the input anywhere from 4 in. (10.2 cm) to 20 in. (50.8 cm) at
SATA 6G speed.
OUTPUT DE-EMPHASIS
The SN75LVCP601 provides the de-emphasis settings shown in Table 1. De-emphasis is controlled
independently for each channel, and is set by the control pins DE1 and DE2 as shown in Table 1. There are two
de-emphasis duration settings available in the device. DEW1 and DEW2 control the DE durations for channels
one and two, respectively. The recommended settings for these control pins are listed Table 1. Output
de-emphasis is capable of supporting FR4 trace at the output anywhere from 2 in. (5.1 cm) to 12 in. (30.5 cm) at
SATA 3G/6G speed.
LOW-POWER MODE
Two low-power modes are supported by the SN75LVCP601, listed as follows:
1. Standby mode (triggered by the EN pin, EN = 0 V)
– Low-power mode is controlled by the enable (EN) pin. In its default state, this pin is internally pulled high.
Pulling this pin LOW puts the device in standby mode within 2 µs (max). In this mode, all active
components of the device are driven to their quiescent level, and differential outputs are driven to Hi-Z
(open). Maximum power dissipation in this mode is 5 mW. Exiting from this mode to normal operation
requires a maximum latency of 5 µs.
6 Copyright © 2010–2012, Texas Instruments Incorporated
SN75LVCP601
www.ti.com
SLLSE41B –JUNE 2010– REVISED FEBRUARY 2012
2. Auto low-power mode (triggered when a given channel is in the electrically idle state for more than 100 µs
and EN = Vcc)
– The device enters and exits low-power mode by actively monitoring the input signal (VIDp-p) level on
each of its channels independently. When the input signal on either or both channels is in the electrically
idle state, that is, VIDp-p < 50 mV and stays in this state for >100 µs, the associated channel(s) enters
into the low-power state. In this state, output of the associated channel(s) is driven to VCM and the
device selectively shuts off some circuitry to lower power by >80% of its normal operating power. Exit
time from the auto low-power mode is <50 ns.
Out-of-Band (OOB) SUPPORT
The squelch detector circuit within the device enables full detection of OOB signaling as specified in the SATA
specification. Differential signal amplitude at the receiver input of 50 mVpp or less is not detected as an activity
and hence not passed to the output. Differential signal amplitude of 150 mVp-p or more is detected as an activity
and therefore passed to the output, indicating activity. Squelch circuit ON/OFF time is 5 ns, maximum. While in
squelch mode, outputs are held to VCM.
DEVICE POWER
The SN75LVCP601 is designed to operate from a single 3.3 V supply. Always practice proper power-supply
sequencing procedure. Apply Vcc first, before any input signals are applied to the device. The power-down
sequence is in reverse order.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage range
Voltage range Differential I/O –0.5 to 4 V
Electrostatic discharge Charged-device model
Continuous power dissipation See Thermal Table
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101-A.
(5) Tested in accordance with JEDEC Standard 22, Test Method A115-A.
(2)
V
CC
Control I/O –0.5 to Vcc + 0.5 V
Human-body model
Machine model
(3)
(4)
(5)
(1)
VALUE UNIT
–0.5 to 4 V
±10,000 V
±1500 V
±200 V
THERMAL INFORMATION
SN75LVCP601
THERMAL METRIC
θ
JA
θ
JCtop
θ
JB
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Product Folder Link(s): SN75LVCP601
(1)
(2)
(3)
(4)
QFN UNITS
20 PINS
38 °C/W
40 °C/W
10 °C/W
SN75LVCP601
SLLSE41B –JUNE 2010– REVISED FEBRUARY 2012
www.ti.com
THERMAL INFORMATION (continued)
SN75LVCP601
THERMAL METRIC
(1)
QFN UNITS
20 PINS
ψ
ψ
θ
P
P
JT
JB
JCbot
D
SD
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
Device power dissipation in active mode 215 to 288 mW
Device power dissipation under standby mode 5 mW
(5)
(6)
(7)
0.5 °C/W
0.9 °C/W
15.2 °C/W
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
(Typical values for all parameters are at VCC= 3.3V and TA= 25°C. All temp limits are specified by design)
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
C
COUPLING
Supply voltage 3 3.3 3.6 V
Coupling capacitor 12 nF
Operating free-air temperature 0 85 °C
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEVICE PARAMETERS
P
D
P
SD
I
CC
I
CC_ALP
I
CC_STDBY
t
PDelay
AutoLP
AutoLP
t
ENB
t
DIS
ENTRY
EXIT
Power dissipation in active mode 215 288 mW
Power dissipation in standby EN = 0 V, DEWx = EQx = DEx = NC, K28.5
mode pattern at 6 Gbps, VID= 700 mV
Active-mode supply current 65 80 mA
Acive power-save mode I
CC
Standby mode supply current EN = 0 V 1 mA
Maximum data rate 1 6 Gbps
Propagation delay Measured using K28.5 pattern. See Figure 8. 323 400 ps
Auto low-power entry time Electrical idle at input; see Figure 9. 80 105 130 µs
Auto low-power exit time After first signal activity; see Figure 9. 42 50 ns
Device enable time EN 0→1 5 µs
Device disable time EN 1→0 2 µs
DEWx = EN = Vcc, EQx = DEx = NC, K28.5
pattern at 6 Gbps, VID= 700 mV
EN = 3.3 V, DEWx= 0 V, EQx/DEx = NC,
K28.5 pattern at 6 Gbps, VID= 700 mV
When device is enabled and auto low-power
conditions are met
p-p
p-p
5 mW
p-p
6.5 10 mA
8 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): SN75LVCP601
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