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SN75LVCP601
User Manual
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Texas instruments SN75LVCP601 User Manual

SN75LVCP601
www.ti.com
SLLSE41 –JUNE 2010
Two-Channel SATA 6-Gb/s Redriver
Check for Samples: SN75LVCP601
1

FEATURES

• Integrated Output Squelch – HBM: 10,000 V
• Programmable Rx/Tx Equalization and – CDM: 1,500 V De-Emphasis Width Control
• Power-Save Feature Lowers Power by >80% in Auto Low-Power Mode

• Low Power APPLICATIONS – <220 mW Typ – <50 mW (in Auto Low-Power Mode) – <5m W (in Standby Mode)

• Excellent Jitter and Loss Compensation Capability to Over 24-Inch (61-cm) FR4 Trace

DESCRIPTION

SN75LVCP601 is a dual-channel, single-lane SATA redriver and signal conditioner supporting data rates up to 6 Gbps. The device complies with SATA physical link 2m and 3i specifications. SN75LVCP601 operates from a single 3.3-V supply and has 100-Ω line termination with a self-biasing feature, making the device suitable for ac coupling. The inputs incorporate an out-of-band (OOB) detector, which automatically squelches the output while maintaining a stable common-mode voltage compliant to the SATA link. The device is also designed to handle spread-spectrum clocking (SSC) transmission per the SATA specification.
The SN75LVCP601 handles interconnect losses at both its input and output. The input stage of each channel offers selectable equalization settings that can be programmed to match the loss in the channel. The differential outputs provide selectable de-emphasis to compensate for the distortion that the SATA signal is expected to experience. The level of equalization and de-emphasis settings depends on the length of interconnect and its characteristics. Both equalization and de-emphasis levels are controlled by the setting of signal control pins EQ1, EQ2, DE1, and DE2.
The device is hot-plug capable (requires the use of ac-coupling capacitors at differential inputs and outputs), preventing device damage under device hot-insertion, such as async signal plug/removal, unpowered plug/removal, powered plug/removal, or surprise plug/removal.
• 20-Pin 4 × 4 QFN Package
– MM: 200 V
• Pin-Compatible to LVCP412A/MAX4951
• Notebooks, Desktops, Docking Stations, Servers. and Workstations
ORDERING INFORMATION
PART NUMBER PART MARKING PACKAGE
SN75LVCP601RTJR LVC601 20-pin RTJ, reel (large) SN75LVCP601RTJT LVC601 20-pin RTJ, reel (small)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testingof all parameters.
(1)
Copyright © 2010, Texas Instruments Incorporated
ICH
R
HDD
eSATA
Cable
eSATA
connector
PC/WSMB
R = SN75LVCP601
ICH
R
Notebook
Dock
Dock Connector
PC/Workstation
Motherboard
NotebookDock
HDD
eSATA Cable
(2m)
eSATA
connector
SATA 6GHost
HDD
DTMB
DesktopMainBoard
iSATA
connector
R
SN75LVCP601
SLLSE41 –JUNE 2010
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
www.ti.com
Figure 1. Typical Application
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Product Folder Link(s): SN75LVCP601
RX1P [1]
CTRL
RT
RT
VBB= 1.7 V TYP
V
BB
RT
RT
Equalizer
Equalizer
Driver
Driver
OOB
Detect
OOB
Detect
SN75LVCP601
TX1P [15]
RX1N [2]
TX1N [14]
RX2N [12]
RX2P [11]
TX2N [4]
TX2P [5]
EN[7]
DE2[8]
DE1[9]
VCC[10,20]
GND[3,13,18]
EQ1[17]
EQ2[19]
DEW1 [16]
DEW2 [6]
SN75LVCP601
www.ti.com
SLLSE41 –JUNE 2010
NAME PIN DESCRIPTION NAME PIN DESCRIPTION
RX1P 1 Input 1, non-inverting RX2P 11 Input 2, non-inverting RX1N 2 Input 1, inverting RX2N 12 Input 2, inverting GND 3 Ground GND 13 Ground TX2N 4 Output 2, inverting TX1N 14 Output 1, inverting TX2P 5 Output 2, non-inverting TX1P 15 Output 1, non-inverting
(1)
DEW2
(1)
EN
(2)
DE2
(2)
DE1 Vcc 10 3.3-V supply Vcc 20 3.3-V supply
(1) DEW1/2, EN tied to Vcc via internal PU resistor (2) DE1, DE2, EQ1, EQ2 are tied to Vcc/2 via internal resistor
6 De-emphasis width cntrl.-CH 2 DEW1 7 Enable EQ1 8 De-emphasis CH2 GND 18 Ground 9 De-emphasis CH1 EQ2
Figure 2. Data Flow Block Diagram
PIN TABLE
(1)
(2)
(2)
16 De-emphasis width cntrl.-CH 1 17 EQ control CH 1
19 EQ control CH 2
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Product Folder Link(s): SN75LVCP601
20
19
18
17
16
6
7
8
9
10
15
14
13
12
11
1
2
3
4
5
RX1P
RX1N
GND
TX2 N
TX2 P
VCC
EN
DE 2
DE 1
DEW 2
RX2P
RX2N
GND
TX1 N
TX1 P
EQ 2
EQ 1
VCC
DEW 1
GND
LVCP601RTJ
Thermal Pad must
be soldered to PCB
GND plane for
efficient thermal
performance
Bottom View
1
1
1
2
1
RX1P
RX1N
GND
TX2 N
TX2 P
DEW 2
DE 1
DE 2
EN
VCC
RX2P
RX2N
GND
TX1 N
TX1 P
VCC
DEW 1
EQ 2
EQ 1
GND
LVCP601RTJ
Top View
18
19
20
10
9
8
7
6
1
2
3
4
5
16
17
11
12
13
14
15
SN75LVCP601
SLLSE41 –JUNE 2010
www.ti.com

PACKAGE PINOUT

PIN FUNCTIONS
PIN
NO. NAME
HIGH-SPEED DIFFERENTIAL I/O
2 RX1N I, CML 1 RX1P I, CML 12 RX2N I, CML 11 RX2P I, CML 14 TX1N O, CML 15 TX1P O, CML 4 TX2N O, CML 5 TX2P O, CML
CONTROL PINS
4 EN I, LVCMOS Device enable/disable pin, internally pulled to Vcc. See Table 2. 8, 9 DE1, DE2 17, 19 EQ1, EQ2 16, 6 DEW1, DEW2 I, LVCMOS De-emphasis width control for CH 1 and CH 2. See Table 2.
POWER
10, 20 Vcc Power Positive supply should be 3.3 V ± 10%. 3, 13, 18 GND Power Supply ground
(1) Internally biased to Vcc/2 with >200-kΩ pullup/pulldown. When 3-state pins are left as NC, board leakage at the pin pad must be <1 µA;
otherwise, drive to Vcc/2 to assert mid-level state.
(1)
(1)
PIN TYPE DESCRIPTION
Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins are tied to an internal voltage bias by a dual-termination resistor circuit.
Non-inverting and inverting CML differential output for CH 1 and CH 2. These pins are internally tied to voltage bias by termination resistors.
I, LVCMOS Selects de-emphasis settings for CH 1 and CH 2 per Table 1. Internally tied to Vcc/2 I, LVCMOS Selects equalization settings for CH 1 and CH 2 per Table 1. Internally tied to Vcc/2
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Product Folder Link(s): SN75LVCP601
16 in. (40.6 cm)
24 in. (61 cm)
SATA Host
Redriver
Redriver on Motherboard
Main Board
SATA Host
Redriver
Dock Board
Redriver on Dock Board
SATA Connector
SATA Connector
16 in. (40.6 cm)
8 in.
(20.3 cm)
8 in.
(20.3 cm)
24 in. (61 cm)
SN75LVCP601
www.ti.com
Table 1. Tx/Rx EQ and DE Pulse-Duration Settings
DE1/DE2 EQ1/EQ2
NC (default) –4 NC (default) 0
0 0 0 7 1 –2 1 14
DEW1/DEW2 Device Function → DE Width for CH1/CH2
0 De-emphasis pulse duration, short (recommended setting when link operates at SATA
1 (default) De-emphasis pulse duration, long (recommended setting when link operates at SATA
CH1/CH2De-Emphasis CH1/CH2Equalization
dB (at 6Gbps) dB (at 6Gbps)
1.5/3/6 Gbps)
1.5/3 Gbps speed only)
Table 2. Control Pin Settings
EN Device Function → Standby Mode
0 Device in standby mode
1 (default) Device enabled
SLLSE41 –JUNE 2010
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5
NOTE: *Trace lengths are suggested values based on TI spice simulations (done over programmable limits of input EQ and
output de-emphasis) to meet SATA loss and jitter spec. Actual trace length supported by the LVCP601 may be more or less than suggested values and depends on board
layout, trace widths, and number of connectors used in the SATA signal path.
Figure 3. Trace Length Example* for LVCP601
Product Folder Link(s): SN75LVCP601
15
14
13
12
11
1
2
3
4
5
3.3 V
LVCP601 RTJ
RX1P
RX1N
TX2N
TX2P
TX1P
TX1N
RX2N
RX2P
10 nF
10 nF
10 nF
10 nF
10 nF
10 nF
10 nF
10 nF
EQ2
EQ1
DEW1
20
19
18
17
16
6
7
8
9
10
1.0 Fm
1.0 Fm
1.0 Fm
SATA Host
SATA
Connector
DEW2
EN
DE1
DE2
Vcc
Vcc
SN75LVCP601
SLLSE41 –JUNE 2010
(1) Place supply capacitors close to device pin. (2) EN can be left open or tied to supply when no external control is implemented. (3) Output de-emphasis selection is set at –2 dB, EQ at 7 dB, and DE duration for SATA I/II/III operation for both
channels.
(4) Actual EQ/DE duration settings depend on device placement relative to host and SATA connector.
Figure 4. Typical Device Implementation
www.ti.com

OPERATION DESCRIPTION

INPUT EQUALIZATION

Each differential input of the SN75LVCP601 has programmable equalization in its front stage. The equalization setting is shown in Table 1. The input equalizer is designed to recover a signal even when no eye is present at the receiver, and effectively supports FR4 trace at the input anywhere from 4 in. (10.2 cm) to 20 in. (50.8 cm) at SATA 6G speed.

OUTPUT DE-EMPHASIS

The SN75LVCP601 provides the de-emphasis settings shown in Table 1. De-emphasis is controlled independently for each channel, and is set by the control pins DE1 and DE2 as shown in Table 1. There are two de-emphasis duration settings available in the device. DEW1 and DEW2 control the DE durations for channels one and two, respectively. The recommended settings for these control pins are listed Table 1. Output de-emphasis is capable of supporting FR4 trace at the output anywhere from 2 in. (5.1 cm) to 12 in. (30.5 cm) at SATA 3G/6G speed.

LOW-POWER MODE

Two low-power modes are supported by the SN75LVCP601, listed as follows:
1. Standby mode (triggered by the EN pin, EN = 0 V) – Low-power mode is controlled by the enable (EN) pin. In its default state, this pin is internally pulled high.
Pulling this pin LOW puts the device in standby mode within 2 µs (max). In this mode, all active components of the device are driven to their quiescent level, and differential outputs are driven to Hi-Z (open). Maximum power dissipation in this mode is 5 mW. Exiting from this mode to normal operation requires a maximum latency of 5 µs.
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