SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Provides Differential SCSI from SingleEnded Controller When Used With the
SN75LBC971A Data Transceiver
D
Designed to Operate at Fast-SCSI Speeds
of 10 Million Data Transfers per Second
D
Nine Transceivers Meet or Exceed the
Requirements of ANSI Standard EIA-485
and ISO-8482 Standards
D
Packaged in Shrink Small-Outline Package
with 25 mil Terminal Pitch
D
Low Disabled Supply Current
22 mA Typ
D
Thermal Shutdown Protection
D
Positive- and Negative-Current Limiting
D
Power-Up/-Down Glitch Protection
description
The SN75LBC970A SCSI differential convertercontrol is an adaptation of the industry’s first
9-channel RS-485 transceiver, the SN75LBC976.
When used in conjunction with one or more of its
companion data transceiver(s), SN75LBC971A,
the chip set provides the superior electrical
performance of differential SCSI from a single-ended SCSI bus controller. A 16-bit, Fast-SCSI bus
can be implemented with just three devices (two
for data and one for control) in the space-efficient,
56-pin, shrink small-outline package (SSOP) and
a few external components.
In a typical differential SCSI node, the SCSI
controller provides the enables for each external
RS-485 transceiver. This could require as many
as 27 additional terminals for a 16-bit differential
bus controller or relegate a 16-bit single-ended
controller to only an 8-bit differential bus. Using the standard nine SCSI control signals, the SN75LBC970A
control transceiver decodes the state of the bus and enables the SN75LBC971A data transceiver(s) to transmit
the single-ended SCSI input signals differentially to the cable or receive the differential cable signals and drive
the single-ended outputs to the controller.
The single-ended SCSI bus interface consists of CMOS bidirectional inputs and outputs. The drivers are rated
at ±16 mA of output current. The receiver inputs are pulled high with approximately 4 mA to eliminate the need
for external pullup resistors for the open-drain outputs of most single-ended SCSI controllers. The single-ended
side of the device is not intended to drive the SCSI bus directly.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RSTFLTR
RESET
DSENS
CLK40
GND
AATN–
TEST
AACK–
TIMEOUT
AREQ–
AC/D–
V
CC
GND
GND
GND
GND
GND
V
CC
DRVBUS
SDB
AMSG–
AI/O–
ASEL–
NC
ABSY–
NC
ARST–
NC
X2
X1/CLK20
NC
BATN–
BATN+
BACK–
BACK+
BREQ–
BREQ+
BC/D–
BC/D+
V
CC
GND
GND
GND
GND
GND
V
CC
BMSG–
BMSG+
BI/O–
BI/O+
BSEL+
BSEL–
BBSY+
BBSY–
BRST+
BRST–
DL PACKAGE
(TOP VIEW)
NC – no internal connection
Terminals 13 through 17 and 40 through 44 are
connected together to the package lead frame and
signal ground.
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The differential SCSI bus interface consists of
bipolar bidirectional inputs and outputs that meet
or exceed the requirements of EIA-485 and ISO
8482-1982/TIA TR30.2 referenced by the American National Standard of Information Systems
(ANSI) X3.131-1994 Small Computer System
Interface-2 (SCSI-2).
The SN75LBC970A is characterized for operation
over the temperature range of 0°C to 70°C.
The SN75LBC970A consists of nine RS-485
differential transceivers, nine TTL- or CMOS-level
compatible transceivers, a state machine and
control logic block, a 20-MHz crystal-controlled
oscillator, a timer, a power-up/-down glitch
protection circuit, and a thermal-shutdown
protection circuit.
The single-ended or controller interface is
designated as the A side and the differential port
is the B side. Since the device uses the SCSI
control signals to decode the state of the bus and
data flow direction, the terminal assignments must
be matched to the corresponding signal on the
SCSI bus. The signal name followed by a minus
sign (–) indicates an active-low signal while a plus
sign (+) indicates an active-high signal.
A reset function, which disables all outputs and
clears internal latches, can be accomplished from
two external inputs and two internally-generated
signals. RESET
(Reset) and DSENS (differential
sense) are available to external circuits for a bus
reset or to disable all outputs should a
single-ended cable be inadvertently connected to
a differential connector. The power-up and
thermal-shutdown are internally generated signals that have the same effect when the supply
voltage is below 3.5 V or the junction temperature
exceeds approximately 175°C.
This data sheet contains descriptions of the
SN75LBC970A input and output signals followed
by the electrical characteristics. The parameter
measurement information is followed by the
theory of operation, a state flow chart, and a
typical circuit in the application information
section.
53
52
BATN–
BATN+
6
51
50
BACK–
BACK+
8
38
37
BMSG–
BMSG+
21
47
46
BC/D–
BC/D+
11
36
35
BI/O–
BI/O+
22
30
29
BRST+
BRST–
27
H
32
31
BBSY+
BBSY–
25
H
34
33
BSEL+
BSEL–
23
H
State Machine and
Control Logic
Oscillator
H
Thermal
Shutdown
Power-Up
and Reset Logic
3
7
2
1
4
55
56
19
DRVBUS
20
SDB
TIMEOUT
AATN–
AACK–
AMSG–
AC/D–
AI/O–
ARST–
ABSY–
ASEL–
49
48
BREQ–
BREQ+
10
AREQ–
9
DSENS
TEST
RESET
RSTFLTR
CLK40
X1/CLK20
X2
logic diagram (positive logic)
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
Logic
NAME NO.
g
Level
I/O
Termination
DESCRIPTION
AACK– 8 TTL I/O Strong pullup SCSI acknowledge (–ACK) signal to/from controller
AATN– 6 TTL I/O Strong pullup SCSI attention (–ATN) signal to/from controller
ABSY– 25 TTL I/O Strong pullup SCSI busy (–BSY) signal to/from the controller
AC/D– 11 TTL I/O Strong pullup SCSI control/data (–C/D) signal to/from the controller
AI/O– 22 TTL I/O Strong pullup SCSI input/output (–I/O) signal to/from the controller
AMSG– 21 TTL I/O Strong pullup SCSI message (–MSG) signal to/from the controller
AREQ– 10 TTL I/O Strong pullup SCSI request (–REQ) signal to/from controller
ARST– 27 TTL I/O Strong pullup SCSI reset (–RST) signal to/from the controller
ASEL– 23 TTL I/O Strong pullup SCSI select (–SEL) signal to/from the controller
BACK– 51 RS-485 I/O Weak pullup SCSI acknowledge (–ACK) signal to/from the bus
BACK+ 50 RS-485 I/O Weak pulldown SCSI acknowledge (+ACK) signal to/from the bus
BATN– 53 RS-485 I/O Weak pullup SCSI attention (–ATN) signal to/from the bus
BATN+ 52 RS-485 I/O Weak pulldown SCSI attention (+ATN) signal to/from the bus
BBSY– 31 RS-485 I/O Weak pulldown SCSI busy (–BSY) signal to/from the bus
BBSY+ 32 RS-485 I/O Weak pullup SCSI busy (+BSY) signal to/from the bus
BC/D– 47 RS-485 I/O Weak pullup SCSI control/data (–C/D) signal to/from the bus
BC/D+ 46 RS-485 I/O Weak pulldown SCSI control/data (+C/D) signal to/from the bus
BI/O– 36 RS-485 I/O Weak pullup SCSI input/output (–I/O) signal to/from the bus
BI/O+ 35 RS-485 I/O Weak pulldown SCSI input/output (+I/O) signal to/from the bus
BMSG– 38 RS-485 I/O Weak pullup SCSI message (–MSG) signal to/from the bus
BMSG+ 37 RS-485 I/O Weak pulldown SCSI message (+MSG) signal to/from the bus
BREQ– 49 RS-485 I/O Weak pullup SCSI request (–REQ) signal to/from the bus
BREQ+ 48 RS-485 I/O Weak pulldown SCSI request (+REQ) signal to/from the bus
BRST– 29 RS-485 I/O Weak pulldown SCSI reset (–RST) signal to/from the bus
BRST+ 30 RS-485 I/O Weak pullup SCSI reset (+RST) signal to/from the bus
BSEL– 33 RS-485 I/O Weak pulldown SCSI select (–SEL) signal to/from the bus
BSEL+ 34 RS-485 I/O Weak pullup SCSI select (+SEL) signal to/from the bus
CLK40 4 CMOS I Strong pulldown 40-MHz clock input
DRVBUS 19 TTL O N/A Driver bus. A high-level logic signal that indicates the SCSI bus is in one of
the information transfer phases.
DSENS 3 TTL I Weak pullup A low-level input initializes the internal latches and disables all drivers.
GND 5, 13–17,
40–44
N/A N/A N/A Supply common
RESET 2 TTL I Weak pullup Reset. A low-level input initializes the internal latches and disables all drivers.
RSTFLTR 1 TTL I Weak pullup Reset filter. Filtered input from the SCSI bus for a system reset. RSTFLTR
differs from RESET by keeping the ARST and BRST drivers enabled.
SDB 20 TTL O N/A A high-level logic signal that indicates a differential to single-ended data flow.
TEST 7 TTL I Weak pulldown Test. A high-level input that places the device in a test mode (see Table 1).
It is grounded during normal operation.
TIMEOUT 9 Analog I/O N/A Time out. This signal connects to an external RC time constant for a time out
during bus arbitration.
V
CC
12, 18, 39, 45 N/A N/A N/A 5-V supply voltage
X1/CLK20 55 CMOS I None 20-MHz crystal oscillator or clock input
X2 56 Analog O None 20-MHz crystal oscillator feedback
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
22 k
200 Ω
Input
V
CC
RSTFLTR
, RESET, AND DSENS
50 kΩ
200 Ω
Input
V
CC
TEST
200 Ω
Input
V
CC
TIMEOUT
200 Ω
Input
V
CC
CLK40
200 Ω
Input
V
CC
A
3 kΩ
12 kΩ
1 kΩ
100 kΩ
B– Pin Only
100 kΩ
B+ Pin Only
18 kΩ
V
CC
Input
B+ AND B–
200 Ω
100 kΩ
X1/CLK20
V
CC
V
CC
X2
X1/CLK20, X2
V
CC
Output
100 kΩ
B– Pin Only
100 kΩ
B+ Pin Only
3 kΩ
12 kΩ
V
CC
Output
A, SDB, DRVBUS B+ AND B–
4 mA
1 kΩ
18 kΩ
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
(see Note 1) –0.3 V to 7V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential bus voltage range (B side) –15 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal-ended bus voltage range (A side and control) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge: B side (see Note 2):Class 2, A: 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Class 2, B: 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All terminals: Class 1, A: 500 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Class 1, B: 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the GND terminals.
2. This absolute maximum rating is tested in accordance with MIL-STD-883C, Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
OPERATING FACTOR
‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
DL 2500 mW 20 mW/°C 1600 mW
‡
This is the inverse of the traditional junction-to-case thermal resistance (R
θJA
).
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
4.75 5 5.25 V
p
A side, DSENS, TEST, RESET, AND RSTFLTR 2
High-level input voltage, V
IH
CLK40 AND X1/CLK20 0.7 V
CC
V
p
A side, DENS, TEST, RESET, and RSTFLTR 0.8
Low-level input voltage, V
IL
CLK40 AND X1/CLK20 0.2 V
CC
V
Input voltage at any bus terminal (separately
12
gy ( y
or common-mode), V
I
B side–7V
Output voltage at any bus terminal (separately
12
gy ( y
or common-mode), V
O
B side–7V
B side –60
High-level output current, I
OH
A side, DRVBUS, SDB, TIMEOUT –16
mA
X2 –4
B side 60
Low-level output current, I
OL
A side, DRVBUS, and SDB 16
mA
X2 4 mA
CLK20 20
Clock frequenc
y,
f
CLK
CLK40 40
MH
z
Operating case temperature, T
C
0 125 °C
Operating free-air temperature, T
A
0 70 °C
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
V
OD(H)
Driver differential
high-level output voltage
B side except BBSY,
BRST, and BSEL
1 1.8 V
V
OD(L)
Driver differential low-level
output voltage
B side
See Figure 1
–1 – 2.2 V
AACK–, AATN–,
AC/D–, AI/O–,
AMSG–, AREQ–
VID = –200 mA,
IOH = –16 mA
2.5 4.3
DRVBUS, SDB IOH = –16 mA 2.5 4.4
V
OH
High-level output voltage
TIMEOUT
Test and RESET at 0.8 V, All
others open, IOH = –16 mA
2.5 4.5
V
B side 3.4
X2 IOH = - 4 mA 3.2
DRVBUS, SDB IOL = 16 mA 0.8
p
A side VID = 200 mV, IOL =16 mA 0.8
VOLLow-level output voltage
B side 1.6
V
X2 IOL = 4 mA 0.8
Receiver positive-going
B side IOH = –16 mA, See Figure 2 0.2
V
IT+
gg
input threshold voltage
TIMEOUT 2.6
V
Receiver negative-going
B side IOL = 16 mA, See Figure 2 –0.2
V
IT–
ggg
input threshold voltage
TIMEOUT
0.32 V
CC
0.4 V
CC
V
Receiver input hysteresis
B side 45 mV
V
hys
y
(V
IT+
– V
IT–
)
TIMEOUT 0.5 V
VI = 12 V, VCC = 5 V,
All other inputs at 0 V
0.6 1
p
VI = 12 V, VCC = 0,
All other inputs at 0 V
0.7 1
IIBus input current
B side
VI = –7 V, VCC = 5 V,
All other inputs at 0 V
–0.5 –0.8
mA
VI = –7 V, VCC = 0,
All other inputs at 0 V
–0.4 –0.8
A side –2.9 –6 –8 mA
DSENS, RESET,
RSTFLTR
V
= 2 V
–60 –100
-
p
CLK40, X1/CLK20
IH
±20
IIHHigh-level in ut current
TEST 100
µA
TIMEOUT
TEST at 2 V, A side and other
control inputs at 0.8 V ,
B side open, VIH = 2 V
±1
A side –6 –8 mA
DSENS, RESET,
RSTFLTR
VIH = 0.8 V
–100
I
IL
Low-level input current
CLK40, TEST,
X1/CLK20
±20
µA
TIMEOUT
TEST at 0.8 V, A side and
other control inputs at 0.8 V ,
B side open, VIH = 2 V
±1
I
OS
Short circuit output current B side VO = 5 V and 0 V ±250 mA
†
All typical values are at VCC = 5 V, TA = 25 °C.
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (Continued)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
Disabled
RESET at 0.8 V,
All others open
27 36
I
CC
Supply current
All A-side to B-side
channels enabled
TEST and RSTFLTR at 2 V
RESET
at 0.8 V,
All other inputs open, no load
72 94
mA
All B-side to A-side
channels enabled
TEST at 2 V, RESET and
RSTFLTR
at 0.8 V,
All other inputs open,
No load
38 50
C
o
Bus output capacitance
B side to GND,
VI = 0.6 sin(2π 106 t)+ 1.5 V
19 21 pF
p
p
B side to A side, one channel 100 pF
CpdPower dissipation capacitance (see Note 3)
A side to B side, one channel 450 pF
†
All typical values are at VCC = 5 V, TA = 25 °C.
NOTE 3: Cpd determines the no-load dynamic current consumption, IS = Cpd × VCC × f + ICC (ICC depends upon the output states and load circuits
and is not necessarily the same ICC as specified in the electrical tables).
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
FROM
(INPUT)TO(OUTPUT)
TEST CONDITIONS MIN TYP†MAX UNIT
AATN–
AC/D–
BATN±
BC/D±
Delay time, A to B,
-
-
AI/O–
AMSG–
BI/O±
BMSG±
See Figure 3
7.6
26.6
t
d1
,
t
d2
high- to low-level or
low- to high-level output
8.5 25.3
ns
g
AACK–
–
BACK±
VCC = 5 V, TA = 25°C 10 18
AREQ
–
BREQ±
VCC = 5 V, TA = 70°C 12.5 20.5
t
sk(lim)
Skew limit
AACK– BACK±
See Note 4 8 ns
t
sk(p)
Pulse skew
AREQ– BREQ±
See Note 5 6 ns
Delay time, B to A,
-
-
BATN±
BC/D±
BI/O±
BMSG±
AATN–
AC/D–
AI/O–
AMSG–
See Figure 4 21.5 36.2
t
d3
,
t
d4
high- to low-level or
low- to high-level output
21.5 36.2
ns
g
BACK±
AACK–
–
VCC = 5 V, TA = 25°C 23.6 32.6
BREQ±
AREQ
–
VCC = 5 V, TA = 70°C 24.4 33.4
t
sk(lim)
Skew limit
BACK± AACK–
See Note 4 9 ns
t
sk(p)
Pulse skew
BREQ± AREQ–
See Note 5 6 ns
t
PHL
Delay time, high- to low-level
200 ns
t
PLH
Delay time, low- to high-level
TIMEOUT
DRVBUS
See Figure 5
200 ns
ABSY– BBSY± 200
t
dis
Disable time
ARST–
BRST±
See Figure 6
200
ns
ASEL– BSEL± 200
ABSY– BBSY± 40
t
en
Enable time
ARST–
BRST±
See Figure 6
55
ns
ASEL– BSEL± 39
t
dis1
Disable time BRST± ARST– 93 ns
t
dis2
Disable time BSEL± ASEL– 55 ns
t
dis3
Disable time BBSY± ABSY– 60 ns
t
en1
Enable time BRST± ARST–
See Figure 7
63 ns
t
en2
Enable time BSEL± ASEL– 45 ns
t
en3
Enable time BBSY± ABSY– 45 ns
t
en4
Enable time BSEL± ASEL– 92 ns
†
All typical values are at VCC = 5 V, TA = 25 °C.
NOTES: 4. This parameter is applicable at one VCC and operating temperature within the recommended operating conditions and to any two
devices.
5. Pulse skew is the difference between the high-to-low and low-to-high propagation delay times of any single channel.
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
5 V
V
OD
VOH, V
OL
VOH, V
OL
165 Ω
165 Ω
75 Ω
VIH, V
IL
BDBn–
BDBn+
A–
2 V
or
0.8 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns PRR ≤1 MHz, 45% < duty cycle
< 50%, ZO = 50 Ω.
B. Resistance values are with a tolerance of 5%.
C. All input voltage levels are held to within 0.01 V.
Figure 1. Differential Driver VOD, VOH, and V
OL
T est Circuit
VID or V
IT
V
I
VOH, V
OL
ADBn–
IOH, I
OL
I
I
BDBn–
BDBn+
Figure 2. Single-Ended Driver VOD, VOH, and V
OL
T est Circuit
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
5 V
Output
165 Ω
165 Ω
75 Ω
Input
(see Note A)
A–
50 pF
50 pF
(see Note B)
B–
B+
t
d1
t
d2
Input Output
0 V
1.5 V
3 V
t0 t0or delay delay
V
OD
A–
RESET
TEST
DSENS
RSTFLTR
V
OD(L)
0 V
V
OD(H)
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns PRR ≤ 1 MHz,
45% < duty cycle < 50%, ZO = 50 Ω.
B. Resistance values are with a tolerance of ±5%.
C. All input voltage levels are held to within 0.01 V.
Figure 3. A-Side to B-Side Propagation Delay Time Test Circuit and Timing Definitions
Output
1.5 V
Input
(see Note A)
B–
15 pF
(see Note B)
t
d3
t
d4
Input Output
0 V
1.5 V
3 V
t0 t0or delay delay
A–
RESET
TEST
DSENS
RSTFLTR
V
OL
1.5 V
V
OH
B+
A–
B–
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns PRR ≤1 MHz, 45% < duty cycle
< 50%, ZO = 50 Ω.
B. Resistance values are with a tolerance of ±5%.
C. All input voltage levels are held to within 0.01 V.
Figure 4. B-Side to A-Side Propagation Delay Time Test Circuit and Timing Definitions
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Table 1. Output Test Enabling (No Clock Input)
SIGNAL BUS CONTROL INPUT(s)
INPUT(s) OUTPUT TEST RSTFLTR RESET BBSY– BBSY+ ABSY– DSENS
ATN, ACK, MSG, C/D, REQ, I/O A B H H L
ATN, ACK, MSG, C/D, REQ, I/O B A H L L
RST A B L—>H H L H H
RST B A L—>H H L H H
SEL, BSY B A L H L—>H H
SEL, BSY B H H L
TIMEOUT N/A H L L
DRVBUS
†
BBSY–/ BBSY+,
BSEL–/BSEL+,
TIMEOUT
DRVBUS H L L
TIMEOUT N/A Z H L
†
For these conditions, DRVBUS = BSEL or BBSY and TIMEOUT together.
Output
Input
TIMEOUT
15 pF
Input Output
0 V
1.5 V
V
CC
t0 t0or t
P
t
P
V
OL
1.5 V
V
OH
DRVBUS
t
PHL
t
PLH
RESET
TEST
DSENS,
BSEL, BBSY
RSTFLTR
TIMEOUT
DRVBUS
Figure 5. TIMEOUT to DRVBUS Delay Time Test Circuit and Timing Definitions
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Input
Output
5 V
50 pF
50 pF
165 Ω
165 Ω
75 Ω
A–
B–
B+
Input Output
0 V
1.5 V
3 V
t0 t0or enable disable
≈ –0.925 V
0.5 V
V
OD(H)
t
en
t
dis
RESET
TEST
DSENS
RSTFLTR
ARST–
ABSY– or ASEL–
CLK20
(see Note A)
t
en
t
dis
BRST
BBSY or BSEL
NOTE A: These are asynchronous events and do not necessarily align with clock edges.
Figure 6. A-Side to B-Side Enable and Disable Delay Time Test Circuit and Timing Definitions
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
en1
t
dis1
RESET
TEST
DSENS
RSTFLTR
Output
1.5 V
Input
B–
15 pF
Input Output
0 V
1.5 V
3 V
t0 t0or delay delay
V
OL
1.5 V
V
OH
B+
A–
t
en3
t
dis3
ООООООООО
t
en2
t
dis2
t
en4
Reset Bus Free
Arbitration
to Select 1
CLK40
(See Note A)
BRST–
BBSY–
BSEL–
ARST–
ABSY–
ASEL–
ООООООООО
ООООООООО
ООООООООО
ООООООООО
ООООООООО
NOTE A: These are asynchronous events and do not necessarily align with clock edges.
Figure 7. B-Side to A-Side Enable and Disable Delay Time Test Circuit and Timing Definitions
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
To correctly set the direction of the SCSI bus signals, the SN75LBC970A must follow the activity on the bus. An
asynchronous, 5-state controller watches the state of all the bus control signals, sets the direction of each control
signal as needed, and generates the DRVBUS and SDB outputs to control one or two external SN75LBC971A SCSI
differential converter-data devices. The controller never generates the data driven on a bus signal; it only enables
the drivers. The clock input implements a 400-ns timer that is not part of the controller itself. Controller-state
transitions occur immediately when all the transition conditions are met. Note that the frequency of the supplied clock,
either 20 MHz or 40 MHz, must be correct in order to meet the SCSI specifications.
As shown in Figure 8, after reset, the controller begins in the bus free state. In case the controller was attached to
an active differential bus, it waits for the SCSI bus free condition, defined as when BBSY and BSEL are deasserted
for 400 ns. While waiting for the SCSI bus free condition, the state of BBSY and BSEL passes through to the A side.
The A side bus device cannot take part in bus activity during this condition before the SCSI bus free condition. Once
SCSI bus free is detected, the SCSI arbitration state is entered. Both ABSY and BBSY are enabled; thus when either
signal asserts, both drivers turn on and both signals remain asserted until this state is left. Normally the SCSI
arbitration state ends after the winner of arbitration asserts BSEL. This would cause the controller to go to the select
1 state. However, when BSEL is not asserted, a timeout would eventually be detected and cause a reset of the
controller. In the select 1 state, two latches are open, DSEL_LATCH and RESEL_LATCH. The first latch captures
the state of BSEL so that following states can determine whether the arbitration winner was on the A side or B side.
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Enable ABSY and ASEL
400 ns of
BBSY = BSEL = 0?
RESET
Enable ABSY and BBSY
Set DSEL_LATCH to BSEL
Set RESEL_LATCH to AI/O
NO
YES
TIMEOUT?
YES
NO
ASEL or
(DSEL_LATCH and
BSEL)?
BBSY?
NO
NO YES
YES
Set RESEL_LATCH to AI/O DSEL_LATCH = 1?
NO
Enable A Side
400 ns of
BBSY = 0?
ABSY = 1 And
BBSY = 0?
NO
NO
ASEL = 1?
Enable B Side
400 ns of
ABSY = 0?
YES
YES
NO
YES
NO
YES
A
RESET
Bus Free
State
SCSI
Arbitration
State
Select 1
State
YES
Continued on Figure 9
SCSI Bus Free Condition
Select 2 State
Figure 8. Bus Free, SCSI Arbitration, and Select 1 State Flow Chart
The second latch captures the state of AI/O. This is true during a reselection phase but not during the selection phase.
When the bus is in the selection or reselection phase, the controller enters the select 1 state. There are three possible
flows depending on bus events. The first flow is that the SCSI controller on the A side won the arbitration and asserted
ASEL. In this event DSEL_LA TCH would not be set. The controller passes all signals to the B side and waits for ABSY
to deassert for 400 ns, indicating that the A side controller is selecting or reselecting a device on the B side. The object
of the A side controller must be on the B side since only one device is allowed on the A side.
The second possible flow is that DSEL_LA TCH is set, indicating that the arbitration winner is on the B side, and the
winner is selecting or reselecting the device on the A side. The controller passes all signals to the A side and waits
for BBSY to deassert for 400 ns. When the A side controller responds by asserting ABSY , the controller detects ABSY
asserted and BBSY deasserts and goes to the select 2 state.
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
The third possible flow is that a device on the B side won the arbitration and is selecting or reselecting another device
on the B side. DSEL_LA TCH is set, and 400 ns of BBSY is asserted first by the object of the selection or reselection.
Since ASEL is still asserted, the controller remains in the select 1 state throughout the selection or reselection. If the
BBSY deassertion is missed by the timer , again the controller remains in the select 1 state. Once the transfer state
is entered, BBSY is asserted and BSEL is dropped. This again returns the controller to a select 1 state. At the end
of the transfer both BBSY and BSEL are deasserted. After the timer limit is reached, the controller goes to the
arbitration state for the next bus arbitration.
The controller enters the select 2 state (see Figure 9) during the selection or reselection phases when the initiator
and terminator are on the opposite side of SDCC. In this state the RESEL_LA TCH is closed, capturing the value of
the I/O. When RESEL_LATCH is one, reselection is indicated. When RESEL_LATCH equals zero, a selection is
indicated. RESEL_LA TCH, along with the DSEL_LATCH, now defines which side the initiator is on and therefore what
direction to establish for all the bus signals. The target must be on the other side; if both target and initiator were on
the B side, the select 2 state would never be entered.
When the RESEL_LATCH is zero, indicating a selection, the connection is not made. When DSEL_LATCH is one,
the initiator is on the B side and the control lines it drives have their A side drivers enabled. These terminals are the
initiator group of ACK and A TN along with SEL. The other terminals are driven by the target and have the B side drivers
enabled. They are the target group of REQ, MSG, C/D, and I/O, along with BSY. When DSEL_LATCH is zero the
connection is reversed. Since transfer states are not started, DRVBUS is set to 1, indicating that the data transceiver
chips should not take their direction control from SDB and should be actively negated. SDB is generated from I/O
and is the bus signal that determines data transfer direction. In this case it indicates the selection phase, the controller
immediately transfers to the transfer state, where exactly the same actions are done.
When the RESEL_LATCH is 1 indicating a reselection, there is one or more actions before information states can
be entered. When the target reselects the initiator, the initiator responds by asserting BSY. Once the connection is
made, the assertion of BSY must be changed over to the target, and the controller must reverse the BSY driver
direction. It does this when SEL deasserts by transferring to the transfer state where the BSY direction is reversed.
In the select 2 state all the control line directions are set as appropriate, except that DRVBUS is not yet asserted. In
the transfer state DRBVUS is set as well.
The controller remains in the transfer state during all other SCSI states. When a bus free state is detected, it goes
back to the arbitration state to wait for the next activity. Note that after BBSY and BSEL deassert, the controller
continues to actively drive the control lines and the data lines through DRVBUS until 400 ns of continuous deassertion
is detected. The drivers are turned off only when the state change occurs.
Figure 10 shows a typical system configuration. The timeout function used in the arbitration state is implemented with
a resistor and capacitor connected to the TIMEOUT
terminal. During reset and whenever the timer is not in use, the
terminal is driven to V
CC
. The timer starts when the driver turns off, allowing the capacitor to charge and the TIMEOUT
terminal to drop to ground. When V
IT-
is reached, the driver turns on, discharging the capacitor and returning
TIMEOUT
to VCC. A timeout event is declared after the driver turns back on and TIMEOUT exceeds V
IT+
.
RST can be asserted on either the A or B side, and is driven to the other side. The drive to the other side is controlled
by a bidirectional latch. When one side asserts, the other side is asserted and a latch is set to that direction. When
the first side deasserts, the driver turns off, but the direction is held until both sides are deasserted. Only then can
the direction change.
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
400 ns of
BBSY = BSEL = 0?
Enable ABSY , AINIT,
BSEL, And BTARG
YES
RESEL_LATCH = 1?
NO
NO
NO
BSEL = 1?
YES
NO
YES
A
YES
Continued From Figure 8
DSEL_LATCH = 1?
YES
Enable BBSY , BINIT,
ASEL, And ATARG
ASEL = 1?
YES
NO
DSEL_LATCH = 1?
DRVBUS = 1
SDB = BI/O
Enable ABSY , A TARG,
BSEL, And BINIT
DRVBUS = 1
SDB = AI/O
Enable BBSY , BT ARG,
ASEL, And AINIT
DSEL_LATCH = 1?
NO
RESEL_LATCH = 1?RESEL_LATCH = 1?
YES
NO
DRVBUS = 1, SDB = BI/O
Enable ABSY , A TARG,
BSEL, And BINIT
DRVBUS = 1, SDB = AI/O
Enable BBSY , BT ARG,
ASEL, And AINIT
YES
YES
Select 2
State
Transfer
State
NO
NO
(On Figure 8)
Select 1 State
Figure 9. SCSI Select 1, Select 2, and Transfer State Flow Chart
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
The SCSI bus signal RST does not directly clear SDCC internal logic. Instead, the RSTFLTR terminal can be
connected as ARST– so that a bus reset clears SDCC. RSTFL TR clears the internal controller but does not clear the
RST bidirectional latch. By connecting these terminals externally through a RC filter as shown in Figure 8, noise
pulses on the bus may be filtered as recommended by the SCSI-2 specification.
SN75LBC970A
3
DSENS
6
±BSY
±SEL
±RST
8
±I/O
±MSG
±C/D
±REQ
4
±ATN
±ACK
7
4
Test
CLK40
(see Note A)
SCSI Controller
–BSY
–SEL
–I/O
–MSG
–C/D
–REQ
–ATN
–ACK
8
–RST
1
2
RESET
(From System)
V
CC
TIMEOUT
55
0.022 µF
205 kΩ
RSTFLTR
RESET
X1/CLK20
X2
DRVBUS SDB
SN75LBC971A
16
2
8
–DB(7–0)
–DBP(0)
RESET
±DB(7–0)
±DBP(0)
DIFFSENS
SN75LBC971A
16
2
8
–DB(15–8)
–DBP(1)
RESET
±DB(15–8)
±DBP(1)
DIFFSENS
20 kΩ
0.1 pF
BBSY±
BSEL±
RST±
DIFFSENS
BI/O±
BMSG±
BC/D±
BREQ±
BATN±
BACK±
ABSY–
ASEL–
AI/O–
AMSG–
AC/D–
AREQ–
AATN–
AACK–
ARST–
20 MHz
(See Note A)
Optional
(See Note B)
DRVBUS
SDB
NOTES: A. When using the 40 MHz clock input, X1 must be connected to VCC.
B. The oscillator cell of the SN75LBC970A is for a series-resonant crystal and needs approximately
10 pF (including fixture capacitance) from X1 and X2 to ground in order to function.
Figure 10. Typical Application of the SN75LBC970A and SN75LBC971A
SN75LBC970A
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS215B – MAY 1995 – REVISED JANUAR Y 1999
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/D 08/97
48-PIN SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.006 (0,15) NOM
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.012 (0,305)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–8°
NOTES: D. All linear dimensions are in inches (millimeters).
E. This drawing is subject to change without notice.
F. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
G. Falls within JEDEC MO-118
IMPORTANT NOTICE
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