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SN75DP128RTQTG4
Datasheet
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Texas Instruments SN75DP128, SN75DP128RTQTG4 Datasheet

Computer/Notebook/DockingStation
GPU
DP++
DP++
DP++
DisplayPort
Enabled
MonitororHDTV
DisplayPort
Enabled
MonitororHDTV
SN75DP128
www.ti.com
SLLS893 – FEBRUARY 2008
DisplayPort 1:2 Switch
1

FEATURES APPLICATIONS

2
• One Input Port to One of Two Output Ports
• Supports Data Rates up to 2.7Gbps
• Supports Dual-Mode DisplayPort
• Output Waveform Mimics Input Waveform
Characteristics
• Enhanced ESD:
– 12kV on all Main Link Pins – 10kV on all Auxiliary Pins
• Enhanced Commercial Temperature Range: 0 ° C to 85 ° C
• 56 Pin 8 × 8 QFN Package

DESCRIPTION

The SN75DP128 is a one Dual-Mode DisplayPort input to one of two Dual-Mode DisplayPort outputs. The outputs will follow the input signal in a manner that provides the highest level of signal integrity while supporting the EMI benefits of spread spectrum clocking. Through the SN75DP128 data rates of up to 2.7Gbps through each link for a total throughput of up to 10.8Gbps can be realized.
In addition to the switching of the DisplayPort high speed signal lines, the SN75DP128 also supports the switching of the bi-directional auxiliary (AUX), Hot Plug Detect (HPD), and Cable Adapter Detect (CAD) channels. The Auxiliary differential pair supports Dual-Mode DisplayPort operation with the ability to be configured as a bi-directional differential bus while in DisplayPort mode or an I2C™ bus while in TMDS mode
The SN75DP128 is characterized for operation over ambient air temperature of 0 ° C to 85 ° C.
• Personal Computer Market
– Desktop PC – Notebook PC – Docking Station – Standalone Video Card

TYPICAL APPLICATION

1
2 I2C is a trademark of Philips Electronics.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2008, Texas Instruments Incorporated
www.ti.com
ML _ B 3 (p )
ML _ B 3 (n )
ML _ B 0 (p )
ML _ B 0 (n )
ML _ IN 2 (p )
ML _ IN 2 (n )
ML _ IN 3 (n )
ML _ IN 3 (p )
ML _ IN 0 (p )
ML _ IN 0 (n )
ML _ IN 1 (p )
ML _ IN 1 (n )
AUX (p )
AUX (n )
AUX _A ( p )
AUX _A ( n )
ML _A 0 ( n)
ML _A 0 ( p)
ML _A 3 ( p)
ML _A 3 ( n)
Receiver
50Ω 50Ω
V
BIAS
AUX _B ( p )
AUX _B ( n )
Priority
HPD _ A
HPD _ B
HPD
CAD
CAD _ A
Receiver
50Ω 50Ω
V
BIAS
Receiver
50Ω 50Ω
V
BIAS
Receiver
50Ω 50Ω
V
BIAS
Driver
Driver
Driver
Driver
Driver
Driver
Driver
Driver
2-to-1
MUX
Switching
Logic
DPVadj
CAD _ B
__
LP
SN75DP128
SLLS893 – FEBRUARY 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

DATA FLOW BLOCK DIAGRAM

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Product Folder Link(s): SN75DP128
www.ti.com
AUX (p)
HPD_B
ML_B 2(n)
ML_B 0(p)
LP
Priority
ML_IN 0(p)
ML_B 3(n)
ML_B 1(p)
ML_IN 1(n)
ML_IN 1(p)
ML_IN 0(n)
ML_IN 3(n)
ML_IN 3(p)
ML_IN 2(n)
ML_IN 2(p)
ML_B 3(p)
GND
VDD
ML_B 1(n)
ML_B 2(p)
VDD
GND
VDD
VDD
AUX_A (p)
AUX_B (p)
VDD
VDD
AUX_A (n)
CAD_B
AUX (n)
GND
ML_B 0(n)
GND
GND
GND
VDD
1
24
23
22
21
20
19
18
17
16
15
141312111098765432
25
26
343332 31 30 29
28
27
40 39
38 37 36 35
48
47
46
45
44
43
42 41
53
56
55
54
52
51
50
49
HPD
VDD
*
1
CAD
HPD_A
CAD_A
GND
ML_A 3(n)
ML_A 3(p)
ML_A 2(n)
ML_A 2(p)
ML_A 1(n)
ML_A 1(p)
VDD
ML_A 0(n)
ML_A 0(p)
GND
AUX_B(n)
DP
Vadj
SN75DP128
SN75DP128
SLLS893 – FEBRUARY 2008
TERMINAL FUNCTIONS
TERMINAL NAME NO. MAIN LINK INPUT PINS
ML_IN 0 3, 4 I DisplayPort Main Link Channel 0 Differential Input ML_IN 1 6, 7 I DisplayPort Main Link Channel 1 Differential Input ML_IN 2 9, 10 I DisplayPort Main Link Channel 2 Differential Input ML_IN 3 12, 13 I DisplayPort Main Link Channel 3 Differential Input
MAIN LINK PORT A OUTPUT PINS
ML_A 0 56, 55 O DisplayPort Main Link Port A Channel 0 Differential Output ML_A 1 53, 52 O DisplayPort Main Link Port A Channel 1 Differential Output ML_A 2 50, 49 O DisplayPort Main Link Port A Channel 2 Differential Output ML_A 3 47, 46 O DisplayPort Main Link Port A Channel 3 Differential Output
MAIN LINK PORT B OUTPUT PINS
ML_B 0 25, 24 O DisplayPort Main Link Port B Channel 0 Differential Output ML_B 1 22, 21 O DisplayPort Main Link Port B Channel 1 Differential Output ML_B 2 19, 18 O DisplayPort Main Link Port B Channel 2 Differential Output ML_B 3 16, 15 O DisplayPort Main Link Port B Channel 3 Differential Output
HOT PLUG DETECT PINS
HPD 37 O Hot Plug Detect Output to the DisplayPort Source HDP_A 40 I Port A Hot Plug Detect Input HPD_B 32 I Port B hot Plug Detect Input
AUXILIARY DATA PINS
AUX 36, 35 I/O Source Side Bidirectional DisplayPort Auxiliary Data Line AUX_A 45, 43 I/O Port A Bidirectional DisplayPort Auxiliary Data Line
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
I/O DESCRIPTION
Product Folder Link(s): SN75DP128
www.ti.com
SN75DP128
SLLS893 – FEBRUARY 2008
TERMINAL FUNCTIONS (continued)
TERMINAL NAME NO.
AUX_B 28, 26 I/O Port B Bidirectional DisplayPort Auxiliary Data Line
CABLE ADAPTER DETECT PINS
CAD 39 O Cable Adapter Detect Output to the DisplayPort Source CAD_A 41 I Port A Cable Adapter Detect Input CAD_B 33 I Port B Cable Adapter Detect Input
CONTROL PINS
LP 30 I Low Power Select Bar Priority 29 I Output Port Priority selection DPVadj 1 I DisplayPort Main Link Output Gain Adjustment
SUPPLY and GROUND PINS
VDD Primary Supply Voltage
*1
VDD GND Ground
2, 8, 14, 17, 23,
34, 48, 54
38 HPD and CAD Output Voltage
5, 11, 20, 27,
42, 44, 51
I/O DESCRIPTION
Table 1. Control Pin Lookup Table
SIGNAL LEVEL
LP
Priority
DP
Vadj
(1) (H) Logic High; (L) Logic Low
(1)
H Normal Mode Normal operational mode for device L Low Power Mode H Port B has Priority If both HPD_A and HPD_B are high, Port B will be selected
L Port A has Priority If both HPD_A and HPD_B are high, Port A will be selected
4.53 k Ω Increased Gain Main Link DisplayPort Output will have an increased voltage swing
6.49 k Ω Normal Gain Main Link DisplayPort Output will have a nominal voltage swing 10 k Ω Decreased Gain Main Link DisplayPort Output will have a decreased voltage swing
STATE DESCRIPTION
Device is forced into a Low Power state causing the outputs to go to a high impedance state. All other inputs are ignored
Explanation of the internal switching logic of the SN75DP128 is located in the Application Information section at the end of the data sheet.
ORDERING INFORMATION
PART NUMBER PART MARKING PACKAGE
SN75DP128RTQR DP128 56-pin QFN Reel (large)
SN75DP128RTQT DP128 56-pin QFN Reel (small)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com .
(1)
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Product Folder Link(s): SN75DP128
www.ti.com
SN75DP128
SLLS893 – FEBRUARY 2008

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)
Supply Voltage Range
(2)
VDD, V Main Link I/O (ML_IN x, ML_A x, ML_B x) Differential Voltage 1.5 V
Voltage Range
HPD and CAD I/O – 0.3 to VDD + 0.3 V Auxiliary I/O – 0.3 to VDD + 0.3 V Control I/O – 0.3 to VDD + 0.3 V Human body model
Electrostatic discharge
Charged-device model Machine model
Continuous power dissipation See Dissipation Rating Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-B (4) Tested in accordance with JEDEC Standard 22, Test Method A115-A
*1
DD
(3)
Auxiliary I/O (AUX +/-, AUX_A +/-, & AUX_B +/-) ± 10000 V All Other Pins ± 12000
(3)
(4)
(1)
VALUE UNIT
– 0.3 to 5.25 V
± 1000 V
± 200 V

DISSIPATION RATINGS

PACKAGE PCB JEDEC TA≤ 25 ° C DERATING FACTOR
56-pin QFN (RTQ)
STANDARD
Low-K 3623 mW 36.23 mW/ ° C 1449 mW
High-K 1109 mW 11.03 mW/ ° C 443.9 mW
ABOVE TA= 25 ° C POWER RATING
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(1)
TA= 85 ° C

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX
R
Junction-to-board thermal 4x4 Thermal vias under powerpad 11.03 ° C/W
θ JB
resistance
R
Junction-to-case thermal 20.4 C/W
θ JC
resistance Device power dissipation
P
D
DisplayPort selected Device power dissipation under low
P
SD
power
(1) The maximum rating is simulated under 5.25 V VDD.
LP = 5V, ML: VID= 600 mV, 2.7 Gbps PRBS; AUX: VID= 500 mV, 1Mbps PRBS; 300 340 mW HPD/CAD A and B = 5V; V
LP = 0V, HPD/CAD A and B = 5V; V

RECOMMENDED OPERATING CONDITIONS

V
DD
V
DD
T
A
MAIN LINK DIFFERENTIAL PINS
V
ID
d
R
R
t
V
Oterm
AUXILIARY PINS
Supply Voltage 4.5 5 5.25 V
*1
HPD and CAD Output reference voltage 1.62 5.25 V Operating free-air temperature 0 85 ° C
Peak-to-peak input differential voltage 0.15 1.4 V Data rate 2.7 Gbps Termination resistance 45 50 55 Ω Output termination voltage 0 2 V
(1)
UNIT
*1
= V
DD
DD
*1
= V
DD
DD
85 µ W
MIN NOM MAX UNIT
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN75DP128
www.ti.com
SN75DP128
SLLS893 – FEBRUARY 2008
RECOMMENDED OPERATING CONDITIONS (continued)
V
I
d
R
HPD, CAD, AND CONTROL PINS
V
IH
V
IL

DEVICE POWER

The SN75DP128 is designed to operate off a single 5V supply.

ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)
I
DD
I
DD
I
SD
Input voltage 0 3.6 V Data rate 1 MHz
High-level input voltage 2 5.25 V Low-level input voltage 0 0.8 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LP = 5V, V
Supply current 60 65 mA
ML: VID= 600 mV, 2.7 Gbps PRBS AUX: VID= 500 mV, 1 Mbps PRBS
*1
= V
DD
DD
HPD/CAD A and B = 5 V
*1
Supply current V
*1
= 5.25 V 0.1 4 mA
DD
Shutdown current LP = 0 V 1 16 µ A
MIN NOM MAX UNIT

HOT PLUG AND CABLE ADAPTER DETECT

The SN75DP128 is designed to support the switching of the Hot Plug Detect and Cable adapter Detect signals. The SN75DP128 has a built in level shifter for the HPD and CAD outputs. The output voltage level of the HPD and CAD pins is defined by the voltage level of the V
*1
pin. Explanation of HPD and the internal logic of the
DD
SN75DP128 is located in the application section at the end of the data sheet.

ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH5
V
OH3.3
V
OH2.5
V
OH1.8
V
OL
I
H
I
L
High-level output voltage IOH= – 100 µ A, V High-level output voltage IOH= – 100 µ A, V High-level output voltage IOH= – 100 µ A, V High-level output voltage IOH= – 100 µ A, V Low-level output voltage IOH= 100 µ A 0 0.4 V High-level input current VIH= 2.0 V, V Low-level input current VIL= 0.8 V, V
*1
= 5 V 4.5 5 V
DD
*1
= 3.3 V 3 3.3 V
DD
*1
= 2.5 V 2.25 2.5 V
DD
*1
= 1.8 V 1.62 1.8 V
DD
= 5.25 V – 10 10 µ A
DD
= 5.25 V – 10 10 µ A
DD

SWITCHING CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PD(CAD)
t
PD(HPD)
t
T1(HPD)
t
T2(HPD)
t
M(HPD)
t
Z(HPD)
Propagation delay V Propagation delay V HPD logic switch pause time V HPD logic switch time V Minimum output pulse duration V Low Power to High-level propagation delay V
*1
= 5 V 5 30 ns
DD
*1
= 5 V 30 110 ns
DD
*1
= 5 V 2 4.7 ms
DD
*1
= 5 V 170 400 ms
DD
*1
= 5 V 100 ns
DD
*1
= 5 V 30 50 110 ns
DD
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Product Folder Link(s): SN75DP128
www.ti.com
DP128
100K Ω100K Ω
HPDInput HPDOutput
0 V
SinkHotPlugDetect
PulseDuration
0 V
Minimum
HotPlugDetect
OutputPulseDuration
HPD_A
HPD
0 V
HPD_B
50%
50%
V
DD
V
DD
*1
t
PD(HPD)
t
m(HPD)
Figure 1. HPD Test Circuit
SN75DP128
SLLS893 – FEBRUARY 2008
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Figure 2. HPD Timing Diagram #1
Product Folder Link(s): SN75DP128
www.ti.com
0 V
SinkHotPlugDetect
Timeout
0V
PortB
Selected
Port A
Selected
HPD
Priority
V
DD
V
DD
HPD_A &HPD_B
V
DD
*1
t
1(HPD)
t
T2(HPD)
0 V
0 V
HPD
0 V
HPD_B
50 %
50 %
V
DD
HPD_A
V
DD
*1
t
Z(HPD)
SN75DP128
SLLS893 – FEBRUARY 2008

Auxiliary Pins

The SN75DP128 is designed to support the 1:2 switching of the bidirectional auxiliary signals in both a differential (DisplayPort) mode and an I2C (DVI, HDMI) mode. The performance of the Auxiliary bus is optimized based on the status of the selected output port ’ s CAD pin.
8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Figure 3. HPD Timing Diagram #2
Figure 4. HPD Timing Diagram #3
Product Folder Link(s): SN75DP128
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