Texas Instruments SN75DP128, SN75DP128RTQTG4 Datasheet

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Computer/Notebook/DockingStation

GPU

DP++

SN75DP128

DP++

DisplayPort

Enabled

MonitororHDTV

DisplayPort

Enabled

MonitororHDTV

SN75DP128

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SLLS893 – FEBRUARY 2008

DisplayPort 1:2 Switch

FEATURES APPLICATIONS

• One Input Port to One of Two Output Ports

• Supports Data Rates up to 2.7Gbps

• Supports Dual-Mode DisplayPort

• Output Waveform Mimics Input Waveform

Characteristics

• Enhanced ESD:

– 12kV on all Main Link Pins – 10kV on all Auxiliary Pins

• Enhanced Commercial Temperature Range: 0 ° C to 85 ° C

• 56 Pin 8 × 8 QFN Package

DESCRIPTION

The SN75DP128 is a one Dual-Mode DisplayPort input to one of two Dual-Mode DisplayPort outputs. The outputs will follow the input signal in a manner that provides the highest level of signal integrity while supporting the EMI benefits of spread spectrum clocking. Through the SN75DP128 data rates of up to 2.7Gbps through each link for a total throughput of up to 10.8Gbps can be realized.

In addition to the switching of the DisplayPort high speed signal lines, the SN75DP128 also supports the switching of the bi-directional auxiliary (AUX), Hot Plug Detect (HPD), and Cable Adapter Detect (CAD) channels. The Auxiliary differential pair supports Dual-Mode DisplayPort operation with the ability to be configured as a bi-directional differential bus while in DisplayPort mode or an I2C™ bus while in TMDS mode

The SN75DP128 is characterized for operation over ambient air temperature of 0 ° C to 85 ° C.

• Personal Computer Market

– Desktop PC – Notebook PC – Docking Station – Standalone Video Card

TYPICAL APPLICATION

2 I2C is a trademark of Philips Electronics.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ML _ B 3 (p )

ML _ B 3 (n )

ML _ B 0 (p )

ML _ B 0 (n )

ML _ IN 2 (p )

ML _ IN 2 (n )

ML _ IN 3 (n )

ML _ IN 3 (p )

ML _ IN 0 (p )

ML _ IN 0 (n )

ML _ IN 1 (p )

ML _ IN 1 (n )

AUX (p )

AUX (n )

AUX _A ( p )

AUX _A ( n )

ML _A 0 ( n)

ML _A 0 ( p)

ML _A 3 ( p)

ML _A 3 ( n)

Receiver

50Ω 50Ω

BIAS

AUX _B ( p )

AUX _B ( n )

Priority

HPD _ A

HPD _ B

HPD

CAD

CAD _ A

Receiver

50Ω 50Ω

BIAS

Receiver

50Ω 50Ω

BIAS

Receiver

50Ω 50Ω

BIAS

Driver

2-to-1

MUX

Switching

Logic

DPVadj

CAD _ B

SN75DP128

SLLS893 – FEBRUARY 2008

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

DATA FLOW BLOCK DIAGRAM

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AUX (p)

HPD_B

ML_B 2(n)

ML_B 0(p)

Priority

ML_IN 0(p)

ML_B 3(n)

ML_B 1(p)

ML_IN 1(n)

ML_IN 1(p)

ML_IN 0(n)

ML_IN 3(n)

ML_IN 3(p)

ML_IN 2(n)

ML_IN 2(p)

ML_B 3(p)

GND

VDD

ML_B 1(n)

ML_B 2(p)

VDD

GND

VDD

AUX_A (p)

AUX_B (p)

VDD

AUX_A (n)

CAD_B

AUX (n)

GND

ML_B 0(n)

GND

VDD

141312111098765432

343332 31 30 29

40 39

38 37 36 35

42 41

HPD

VDD

CAD

HPD_A

CAD_A

GND

ML_A 3(n)

ML_A 3(p)

ML_A 2(n)

ML_A 2(p)

ML_A 1(n)

ML_A 1(p)

VDD

ML_A 0(n)

ML_A 0(p)

GND

AUX_B(n)

Vadj

SN75DP128

SLLS893 – FEBRUARY 2008

TERMINAL FUNCTIONS

TERMINAL NAME NO. MAIN LINK INPUT PINS

ML_IN 0 3, 4 I DisplayPort Main Link Channel 0 Differential Input ML_IN 1 6, 7 I DisplayPort Main Link Channel 1 Differential Input ML_IN 2 9, 10 I DisplayPort Main Link Channel 2 Differential Input ML_IN 3 12, 13 I DisplayPort Main Link Channel 3 Differential Input

MAIN LINK PORT A OUTPUT PINS

ML_A 0 56, 55 O DisplayPort Main Link Port A Channel 0 Differential Output ML_A 1 53, 52 O DisplayPort Main Link Port A Channel 1 Differential Output ML_A 2 50, 49 O DisplayPort Main Link Port A Channel 2 Differential Output ML_A 3 47, 46 O DisplayPort Main Link Port A Channel 3 Differential Output

MAIN LINK PORT B OUTPUT PINS

ML_B 0 25, 24 O DisplayPort Main Link Port B Channel 0 Differential Output ML_B 1 22, 21 O DisplayPort Main Link Port B Channel 1 Differential Output ML_B 2 19, 18 O DisplayPort Main Link Port B Channel 2 Differential Output ML_B 3 16, 15 O DisplayPort Main Link Port B Channel 3 Differential Output

HOT PLUG DETECT PINS

HPD 37 O Hot Plug Detect Output to the DisplayPort Source HDP_A 40 I Port A Hot Plug Detect Input HPD_B 32 I Port B hot Plug Detect Input

AUXILIARY DATA PINS

AUX 36, 35 I/O Source Side Bidirectional DisplayPort Auxiliary Data Line AUX_A 45, 43 I/O Port A Bidirectional DisplayPort Auxiliary Data Line

I/O DESCRIPTION

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SN75DP128

SLLS893 – FEBRUARY 2008

TERMINAL FUNCTIONS (continued)

TERMINAL NAME NO.

AUX_B 28, 26 I/O Port B Bidirectional DisplayPort Auxiliary Data Line

CABLE ADAPTER DETECT PINS

CAD 39 O Cable Adapter Detect Output to the DisplayPort Source CAD_A 41 I Port A Cable Adapter Detect Input CAD_B 33 I Port B Cable Adapter Detect Input

CONTROL PINS

LP 30 I Low Power Select Bar Priority 29 I Output Port Priority selection DPVadj 1 I DisplayPort Main Link Output Gain Adjustment

SUPPLY and GROUND PINS

VDD Primary Supply Voltage

VDD GND Ground

2, 8, 14, 17, 23,

34, 48, 54

38 HPD and CAD Output Voltage

5, 11, 20, 27,

42, 44, 51

I/O DESCRIPTION

Table 1. Control Pin Lookup Table

SIGNAL LEVEL

Priority

Vadj

(1) (H) Logic High; (L) Logic Low

(1)

H Normal Mode Normal operational mode for device L Low Power Mode H Port B has Priority If both HPD_A and HPD_B are high, Port B will be selected

L Port A has Priority If both HPD_A and HPD_B are high, Port A will be selected

4.53 k Ω Increased Gain Main Link DisplayPort Output will have an increased voltage swing

6.49 k Ω Normal Gain Main Link DisplayPort Output will have a nominal voltage swing 10 k Ω Decreased Gain Main Link DisplayPort Output will have a decreased voltage swing

STATE DESCRIPTION

Device is forced into a Low Power state causing the outputs to go to a high impedance state. All other inputs are ignored

Explanation of the internal switching logic of the SN75DP128 is located in the Application Information section at the end of the data sheet.

ORDERING INFORMATION

PART NUMBER PART MARKING PACKAGE

SN75DP128RTQR DP128 56-pin QFN Reel (large)

SN75DP128RTQT DP128 56-pin QFN Reel (small)

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com .

(1)

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SN75DP128

SLLS893 – FEBRUARY 2008

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply Voltage Range

(2)

VDD, V Main Link I/O (ML_IN x, ML_A x, ML_B x) Differential Voltage 1.5 V

Voltage Range

HPD and CAD I/O – 0.3 to VDD + 0.3 V Auxiliary I/O – 0.3 to VDD + 0.3 V Control I/O – 0.3 to VDD + 0.3 V Human body model

Electrostatic discharge

Charged-device model Machine model

Continuous power dissipation See Dissipation Rating Table

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-B (4) Tested in accordance with JEDEC Standard 22, Test Method A115-A

(3)

Auxiliary I/O (AUX +/-, AUX_A +/-, & AUX_B +/-) ± 10000 V All Other Pins ± 12000

(3)

(4)

(1)

VALUE UNIT

– 0.3 to 5.25 V

± 1000 V

± 200 V

DISSIPATION RATINGS

PACKAGE PCB JEDEC TA≤ 25 ° C DERATING FACTOR

56-pin QFN (RTQ)

STANDARD

Low-K 3623 mW 36.23 mW/ ° C 1449 mW

High-K 1109 mW 11.03 mW/ ° C 443.9 mW

ABOVE TA= 25 ° C POWER RATING

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

(1)

TA= 85 ° C

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX

Junction-to-board thermal 4x4 Thermal vias under powerpad 11.03 ° C/W

θ JB

resistance

Junction-to-case thermal 20.4 C/W

θ JC

resistance Device power dissipation

DisplayPort selected Device power dissipation under low

power

(1) The maximum rating is simulated under 5.25 V VDD.

LP = 5V, ML: VID= 600 mV, 2.7 Gbps PRBS; AUX: VID= 500 mV, 1Mbps PRBS; 300 340 mW HPD/CAD A and B = 5V; V

LP = 0V, HPD/CAD A and B = 5V; V

RECOMMENDED OPERATING CONDITIONS

MAIN LINK DIFFERENTIAL PINS

Oterm

AUXILIARY PINS

Supply Voltage 4.5 5 5.25 V

HPD and CAD Output reference voltage 1.62 5.25 V Operating free-air temperature 0 85 ° C

Peak-to-peak input differential voltage 0.15 1.4 V Data rate 2.7 Gbps Termination resistance 45 50 55 Ω Output termination voltage 0 2 V

(1)

UNIT

= V

85 µ W

MIN NOM MAX UNIT

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SN75DP128

SLLS893 – FEBRUARY 2008

RECOMMENDED OPERATING CONDITIONS (continued)

HPD, CAD, AND CONTROL PINS

DEVICE POWER

The SN75DP128 is designed to operate off a single 5V supply.

ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

Input voltage 0 3.6 V Data rate 1 MHz

High-level input voltage 2 5.25 V Low-level input voltage 0 0.8 V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LP = 5V, V

Supply current 60 65 mA

ML: VID= 600 mV, 2.7 Gbps PRBS AUX: VID= 500 mV, 1 Mbps PRBS

= V

HPD/CAD A and B = 5 V

Supply current V

= 5.25 V 0.1 4 mA

Shutdown current LP = 0 V 1 16 µ A

MIN NOM MAX UNIT

HOT PLUG AND CABLE ADAPTER DETECT

The SN75DP128 is designed to support the switching of the Hot Plug Detect and Cable adapter Detect signals. The SN75DP128 has a built in level shifter for the HPD and CAD outputs. The output voltage level of the HPD and CAD pins is defined by the voltage level of the V

pin. Explanation of HPD and the internal logic of the

SN75DP128 is located in the application section at the end of the data sheet.

ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OH5

OH3.3

OH2.5

OH1.8

High-level output voltage IOH= – 100 µ A, V High-level output voltage IOH= – 100 µ A, V High-level output voltage IOH= – 100 µ A, V High-level output voltage IOH= – 100 µ A, V Low-level output voltage IOH= 100 µ A 0 0.4 V High-level input current VIH= 2.0 V, V Low-level input current VIL= 0.8 V, V

= 5 V 4.5 5 V

= 3.3 V 3 3.3 V

= 2.5 V 2.25 2.5 V

= 1.8 V 1.62 1.8 V

= 5.25 V – 10 10 µ A

SWITCHING CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PD(CAD)

PD(HPD)

T1(HPD)

T2(HPD)

M(HPD)

Z(HPD)

Propagation delay V Propagation delay V HPD logic switch pause time V HPD logic switch time V Minimum output pulse duration V Low Power to High-level propagation delay V

= 5 V 5 30 ns

= 5 V 30 110 ns

= 5 V 2 4.7 ms

= 5 V 170 400 ms

= 5 V 100 ns

= 5 V 30 50 110 ns

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DP128

100K Ω100K Ω

HPDInput HPDOutput

0 V

SinkHotPlugDetect

PulseDuration

0 V

Minimum

HotPlugDetect

OutputPulseDuration

HPD_A

HPD

0 V

HPD_B

50%

PD(HPD)

m(HPD)

Figure 1. HPD Test Circuit

SN75DP128

SLLS893 – FEBRUARY 2008

Figure 2. HPD Timing Diagram #1

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0 V

SinkHotPlugDetect

Timeout

PortB

Selected

Port A

Selected

HPD

Priority

HPD_A &HPD_B

1(HPD)

T2(HPD)

0 V

HPD

0 V

HPD_B

50 %

HPD_A

Z(HPD)

SN75DP128

SLLS893 – FEBRUARY 2008

Auxiliary Pins

The SN75DP128 is designed to support the 1:2 switching of the bidirectional auxiliary signals in both a differential (DisplayPort) mode and an I2C (DVI, HDMI) mode. The performance of the Auxiliary bus is optimized based on the status of the selected output port ’ s CAD pin.

Figure 3. HPD Timing Diagram #2

Figure 4. HPD Timing Diagram #3

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ELECTRICAL CHARACTERISTICS

100Ω

3.3V

100KΩ

3.3V

50Ω 50Ω

10 pF 0.5 pF

CAD = 0

AUX+

AUX-

SN 75 DP 128

AUX

+ or -

3.3 V

100 KΩ

3.3 V

2 KΩ

10 pF 50 pF

CAD = 1

SN75DP128

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V I

C C r

ON(C0)

Δ r r

ON(C1)

Maximum passthrough voltage (CAD=1) V

Pass1

Output current from unselected output V I/O capacitance when in low power DC bias = 1 V, AC = 1.4 Vp-p, F = 100 kHz, 9 12 pF

IO(off)

I/O capacitance when in normal operation 18 25 pF

IO(on)

On resistance V On resistance V

On resistance V

DD DD

DC bias = 1 V, AC = 1.4 Vp-p, F = 100 kHz, CAD = High

DD DD DD

SWITCHING CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

sk(AUX)

L(AUX)

PLH(AUXC0)

PHL(AUXC0)

PLH(AUXC1)

PHL(AUXC1)

Intra-pair skew VID= 400 mV, VIC= 2 V 40 80 ps Single Line Insertion Loss VID= 500 mV, VIC= 2 V, F = 1 MHz, CAD = Low 0.4 dB Propagation delay time, low to high CAD = Low, F = 1 MHz 3 ps Propagation delay time, high to low CAD = Low, F = 1 MHz 3 ps Propagation delay time, low to high CAD = High, F = 100 kHz 3 ns Propagation delay time, high to low CAD = High, F = 100 kHz 3 ns

SN75DP128

SLLS893 – FEBRUARY 2008

= 4.5 V, VI= 5 V, IO= 100 µ A 2.4 3.6 V = 5.25 V, VO= 0 – 3.6 V, VI= 0 V – 5 5 µ A

= 4.5 V, VI= 0 – 3.6 V, IO= 5 mA, CAD = Low 3.5 10 Ω = 4.5 V, VI= 0 – 3.6 V, IO= 5 mA, CAD = Low 1 5 Ω = 4.5 V, VI= 0.4 V, IO= 3 mA, CAD = High 10 18 Ω

Figure 5. Auxiliary Channel Test Circuit (CAD = LOW)

Figure 6. Auxiliary Channel Test Circuit (CAD = HIGH)

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2. 2 V

1. 8 V

50 %

sk(AUX)

2.2V

1.8V

0 V

Differential AUXInput

Differential

AUXOutput

AUXInput

PHL(AUXC0)

PLH(AUXC0)

1 V

AUX

Input

+ or -

AUX

Output

+ or -

PHL(AUX1)

PLH(AUX1)

SN75DP128

SLLS893 – FEBRUARY 2008

Figure 7. Auxiliary Channel Skew Measurement

Figure 8. Auxiliary Channel Delay Measurement (CAD = LOW)

Figure 9. Auxiliary Channel Delay Measurement (CAD = HIGH)

Main Link Pins

The SN75DP128 is designed to support the 1:2 switching of DisplayPort ’ s high speed differential main link. The main link I/O of the SN75DP128 are designed to track the magnitude and frequency characteristics of the input waveform and replicate them on the output. A feature has also been incorporated in the SN75DP128 to either increase or decrease the output amplitude via the resistor connected between the DPVADJ pin and ground.

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ELECTRICAL CHARACTERISTICS

Driver

50 W

Receiver

D+

D-

D+

D-

0.5 pF

100 pF

0Vto2V

Iterm

50 W

V =V -V

V =(V +V )

ID D+ D-

ICM D+ D-

V =V -V

V =(V +V )

OD Y Z

OC Y Z

Output

Input

InputEdgeRate

20% to 80%

80 ps

R/FDP

I/O

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Δ V

I/O(2)

Δ V

I/O(3)

Δ V

I/O(4)

Δ V

I/O(6)

INT

Iterm

Difference between input and output) voltages

– VID)

Input termination impedance 45 50 55 Ω Input termination voltage 0 2 V

SWITCHING CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R/F(DP)

SK(1)

SK(2)

DPJIT(PP)

Output edge rate (20% – 80%) Input edge rate = 80 ps (20% – 80%) 115 160 ps Propagation delay time F= 1 MHz, VID= 400 mV 200 240 280 ps Intra-pair skew F= 1 MHz, VID= 400 mV 20 ps Inter-pair skew F= 1 MHz, VID= 400 mV 40 ps Peak-to-peak output residual jitter dR= 2.7 Gbps, VID= 400 mV, PRBS 27-1 25 35 ps

VID= 200 mV, DPV VID= 300 mV, DPV VID= 400 mV, DPV VID= 600 mV, DPV

SLLS893 – FEBRUARY 2008

= 6.5 k Ω 0 30 60 mV

adj

= 6.5 k Ω – 24 11 36 mV

adj

= 6.5 k Ω – 45 – 15 15 mV

adj

= 6.5 k Ω – 87 – 47 – 22 mV

adj

SN75DP128

Figure 10. Main Link Test Circuit

Figure 11. Main Link Δ V

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and Edge Rate Measurements

I/O

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ML_INx+

ML_INx-

0 V

MainLink

Input

MainLink

Output

PD(ML)

ML x+

ML x-

50%

sk1

2.2V

1.8V

50%

sk1

2.2V

1.8V

ML y+

ML y-

sk2

SN75DP128

SLLS893 – FEBRUARY 2008

Figure 12. Main Link Delay Measurements

Figure 13. Main Link Skew Measurements

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V − SupplyVoltageDD− V

DV − Input/OutputVoltage − mV

I/O

-20

-10

4.4 4.6 4.8 5 5.2 5.4

V =200mV

V =300mV

V =400mV

V =600mV

Temp=25 C

−150

−100

−50

100

150

DP − Resistance

Vadj

− W

DV − Input/OutputVoltage − mV

I\O

0 10k 12k2k 4k 6k 8k 14k

V =200mV

V =300mV

V =400mV

V =600mV

Temp=25 C

InputEdgeRate20%-80%(ps)

OutputEdgeRate20%-80%(ps)

100

120

140

160

180

200

0 50 100 150 200

V =5.25V,85 C

V =5VDD,25 C

V =4.5VDD,0 C

200

210

230

260

270

280

300

DataRate − Bps

P − PowerDissipation − mW

0 2G 2.5G500M 1G 1.5G 3G

85 C

290

250

240

220

0 C

25 C

SN75DP128

SLLS893 – FEBRUARY 2008

TYPICAL CHARACTERISTICS

INPUT/OUTPUT VOLTAGE INPUT/OUTPUT VOLTAGE

vs vs

RESISTANCE SUPPLY VOLTAGE

Figure 14. Figure 15.

INPUT EDGE RATE POWER DISSIPATION

vs vs

OUTPUT EDGE RATE DATA RATE

Figure 16. Figure 17.

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Priority

HPD_A

HPD_B

HPD_OUT

Channel A

ChannelB

HI-Z

SN75DP128

SLLS893 – FEBRUARY 2008

APPLICATION INFORMATION

SWITCHING LOGIC

The switching logic of the SN75DP128 is tied to the state of the HPD input pins as well as the priority pin and low power pin. When both HPD_A and HPD_B input pins are LOW, the SN75DP128 enters the low power state. In this state the outputs are high impedance, and the device is shutdown to optimize power conservation. When either HPD_A or HPD_B goes high, the device enters the normal operational state, and the port associated with the HPD pin that went high is selected. If both HPD_A and HPD_B are HIGH, the port selection is determined by the state of the priority pin.

Several key factors were taken into consideration with this digital logic implementation of channel selection as well as HPD repeating. This logic has been divided into the following four scenarios.

1. Low power state to active state. There are two possible cases for this scenario depending on the state of the low power pin:

– Case one: In this case both HPD inputs are initially LOW and the low power pin is also LOW. In this initial

state the device is in a low power mode. Once one of the HPD inputs goes to a HIGH state, the device remains in the low power mode with both the main link and auxiliary I/O in a high impedance state. However, the port associated with the HPD input that went HIGH is still selected and the HPD output to the source is enabled and follows the logic state of the input HPD (see Figure 18 ). The state of the Priority pin has no effect in this scenario as only one HPD input port is active.

– Case two: In this case both HPD inputs are initially LOW and the low power pin is HIGH. In this initial

state the device is in a low power mode. Once one of the HPD inputs goes to a HIGH state, the device comes out of the low power mode and enters active mode enabling the main link and auxiliary I/O. The port associated with the HPD input that went HIGH is selected and the HPD output to the source is enabled and follows the logic state of the input HPD (see Figure 19 ). This is specified as t state of the Priority pin has no effect in this scenario as only one HPD input port is active.

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Figure 18.

. Again,the

Z(HPD)

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Priority

HPD_A

HPD_B

HPD_OUT

Channel A

ChannelB

HI-Z

DATA

Priority

HPD_A

HPD_B

HPD_OUT

Channel A

ChannelB

HI-Z

DATA

SN75DP128

SLLS893 – FEBRUARY 2008

Figure 19.

2. HPD Changes on the selected port. There are also two possible starting cases for this scenario: – Case one: In this case only one HPD input is initially HIGH. The HPD output logic state follows the state

of the HPD input. If the HPD input pulses LOW, as may be the case if the Sink device is requesting an interrupt, the HPD output to the source also pulses LOW for the same duration of time with a slight delay (see Figure 20 ). The delay of this signal through the SN75DP128 is specified as t the LOW pulse is less then t LOW pulse exceeds t

T2(HPD)

, it may not be accurately repeated to the source. If the duration of the

M(HPD)

, the device assumes that an unplug event has occurred and enters the low

PD(HPD)

. If the duration of

power state (see Figure 21 ). Once the HPD input goes high again, the device returns to the active state as indicated in scenario 1. The state of the Priority pin has no effect in this scenario as only one HPD input port is active.

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Figure 20.

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Priority

HPD_A

HPD_B

HPD_OUT

Channel A

ChannelB

HI-Z

DATA

Priority

HPD_A

HPD_B

HPD_OUT

Channel A

ChannelB

HI-Z

DATA

SN75DP128

SLLS893 – FEBRUARY 2008

Figure 21.

– Case two: In this case both HPD inputs are initially HIGH and the selected port has been determined by

the state of the priority pin. The HPD output logic state follows the state of the selected HPD input. If the HPD input pulses LOW, the HPD output to the source also pulses LOW for the same duration of time, again with a slight delay (see Figure 22 ). If the duration of the LOW pulse exceeds t

T2(HPD)

assumes that an unplug event has occurred and the other port is selected (see Figure 23 ). The case in which the previously selected port with priority goes high again is covered in scenario 3.

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Figure 22.

, the device

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Priority

HPD_A

HPD_B

HPD_OUT

Channel A

ChannelB

HI-Z

DATA HI-Z

DATA

Priority

HPD_A

HPD_B

HPD_OUT

Channel A

ChannelB

HI-Z

DATA

SN75DP128

SLLS893 – FEBRUARY 2008

Figure 23.

3. One channel becomes active while other channel is already selected. There are also two possible starting cases for this scenario:

– Case one: In this case the HPD input that is initially HIGH is from the port that has priority. Since the port

with priority is already selected, any activity on the HPD input from the other port doesnot have any effect on the switch whatsoever (see Figure 24 ).

Figure 24.

– Case two: In this case the HPD input that is initially HIGH is not the port with priority. When the HPD input

of the port that has priority goes high, the HPD output is forced LOW for some time in order to simulate an unplug event to the source device. The duration of this LOW output is defined as t input of the port with priority pulses LOW for a short duration while the t

T2(HPD)

timer is counting down, the

T2(HPD)

timer is reset. Once this time has passed the switch switches to the port with priority and the output HPD

Product Folder Link(s): SN75DP128

. If the HPD

www.ti.com

Priority

HPD_A

HPD_B

HPD_OUT

Channel A

ChannelB

HI-Z

DATA HI-Z

DATA

Priority

HPD_A

HPD_B

HPD_OUT

Channel A

ChannelB

HI-Z

DATA

SN75DP128

SLLS893 – FEBRUARY 2008

once again follows the state of the newly selected channel ’ s HPD input (see Figure 25 ).

Figure 25.

4. 4. Priority pin is toggled. There are also two possible starting cases for this scenario: – Case one: In this case only one HPD input is HIGH. A port whose HPD input is LOW cannot be selected.

In this case, the state of the priority pin has no effect on the switch (see Figure 26 ).

– Case two: In this case both HPD inputs are HIGH. Changing the state of the priority pin when both HPD

Figure 26.

inputs are high forces the device to switch which channel is selected. When a state change is detected on

the priority pin, the device waits for a short period of time t

T1(HPD)

before responding (see Figure 27 ). The purpose for this pause is to allow for the priority signal to settle and also to allow the device to ignore potential glitches on the priority pin. Once t

T1(HPD)

has expired, the HPD output is forced LOW for t

and the device follows the chain of events outlined in scenario 3 case 2.

Product Folder Link(s): SN75DP128

T2(HPD)

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Priority

HPD_A

HPD_B

HPD_OUT

Channel A

ChannelB

HI-Z

DATA HI-Z

DATA

SN75DP128

SLLS893 – FEBRUARY 2008

Figure 27.

Product Folder Link(s): SN75DP128

PACKAGE OPTION ADDENDUM

www.ti.com

20-Mar-2008

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

SN75DP128RTQR ACTIVE QFN RTQ 56 2000 Green (RoHS &

no Sb/Br)

SN75DP128RTQRG4 ACTIVE QFN RTQ 56 2000 Green (RoHS &

no Sb/Br)

SN75DP128RTQT ACTIVE QFN RTQ 56 250 Green (RoHS &

no Sb/Br)

SN75DP128RTQTG4 ACTIVE QFN RTQ 56 250 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-3-260C-168 HR

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

Type

SN75DP128RTQR QFN RTQ 56 2000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2 SN75DP128RTQT QFN RTQ 56 250 180.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN75DP128RTQR QFN RTQ 56 2000 346.0 346.0 33.0

SN75DP128RTQT QFN RTQ 56 250 190.5 212.7 31.8

Pack Materials-Page 2

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Texas Instruments SN75DP128, SN75DP128RTQTG4 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES APPLICATIONS

DESCRIPTION

TYPICAL APPLICATION

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DATA FLOW BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

THERMAL CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

DEVICE POWER

ELECTRICAL CHARACTERISTICS

HOT PLUG AND CABLE ADAPTER DETECT

ELECTRICAL CHARACTERISTICS

SWITCHING CHARACTERISTICS

Auxiliary Pins

ELECTRICAL CHARACTERISTICS

SWITCHING CHARACTERISTICS

Main Link Pins

ELECTRICAL CHARACTERISTICS

SWITCHING CHARACTERISTICS

TYPICAL CHARACTERISTICS

APPLICATION INFORMATION

SWITCHING LOGIC