Texas Instruments SN75DP122, SN75DP122RTQTG4 Datasheet

1

FEATURES

APPLICATIONS

DESCRIPTION

TYPICAL APPLICATION

Computer/Notebook/DockingStation

GPU

DP++

SN75DP122

DP++

TMDS

DisplayPort

Enabled

MonitororHDTV

HDMI / DVI

MonitororHDTV

SN75DP122

SLLS892 – FEBRUARY 2008

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DisplayPort 1:2 Switch With Integrated TMDS Translator

• One Input Port to One of Two Output Ports – 12 kV on all High Speed Pins

• Integrated TMDS Level Translator with – 8 kV on all Auxiliary and I2C Pins

Receiver Equalization

• Enhanced Commercial Temperature Range:

• DP Port Supports Data Rates up to 2.7 Gbps

0 ° C to 85 ° C

• DP Port Supports Dual-Mode DisplayPort

• 56 Pin 8 × 8 QFN Package

• DP Port Output Waveform Mimics Input

Waveform Characteristics

• Personal Computer Market

• TMDS Port Supports Data Rates up to 2.5

– Desktop PC

Gbps

– Notebook PC

• Integrated I2C Logic Block for DVI/HDMI

– Docking Station

Connector Recognition

– Standalone Video Card

• Enhanced ESD:

The SN75DP122 is a one Dual-Mode DisplayPort input to one Dual-Mode DisplayPort output or one TMDS
output. The TMDS output has a built in level translator compliant with Digital Video Interface (DVI) 1.0 and High
Definition Multimedia Interface (HDMI) 1.3b. The DisplayPort output follows the input signal in a manner that
provides the highest level of signal integrity while supporting the EMI benefits of spread spectrum clocking.
Through the SN75DP122 data rates of up to 2.7 Gbps through each link for a total throughput of up to 10.8 Gbps
can be realized.

In addition to the switching of the DisplayPort high speed signal lines, the SN75DP122 also supports the
switching of the bidirectional auxiliary (AUX), Hot Plug Detect (HPD), and Cable Adapter Detect (CAD) channels.
The Auxiliary differential pair supports Dual-Mode DisplayPort operation through the DisplayPort port. Through
the TMDS port the auxiliary port is configured as an I2C port with an integrated I2C repeater.

The SN75DP122 is characterized for operation over ambient air temperature of 0 ° C to 85 ° C.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2008, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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DATA FLOW BLOCK DIAGRAM

ML_IN 2(p)

ML_IN 2(n)

ML_IN 3(n)

ML_IN 3(p)

ML_IN 0(p)

ML_IN 0(n)

ML_IN 1(p)

ML_IN 1(n)

AUX(p)_I2C (SCL)

AUX(n)_I2C (SDA)

AUX_SINK (p)

AUX_SINK (n)

I2C_SCL

I2C_SDA

DP_SINK 0(n)

DP_SINK 0(p)

DP_SINK 3(p)

DP_SINK 3(n)

TMDS_SINK_CLK (p)

V

Sadj

Receiver

50 W

V

BIAS

I2C_SCL

I2C_SDA

TMDS_SINK_CLK (n)

TMDS_SINK 2(p)

TMDS_SINK 2(n)

Priority

DP_HPD_SINK

TMDS_HPD_SINK

HPD

CAD

CAD_SINK

Receiver

V

BIAS

Receiver

V

BIAS

Receiver

V

BIAS

Driver

Driver

Driver

Driver

Driver

Driver

Driver

Driver

2-to-1

MUX

Switching

Logic

I2CLogic

DP

Vadj

__
LP

50 W

50 W

50 W

50 W

50 W

50 W

50 W

SN75DP122

SLLS892 – FEBRUARY 2008

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

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VCC

VDD

GND

GND

GND

VCC

1

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

76

5432

25

26

34

33

32

31

30

29

28

27

40 39

38

37

36

35

48

47

46

45

44

43

42 41

53

56

55

54

52

51

50

49

VDD

GND

VSadj

AUX_SINK(n)

AUX_SINK(p)

DP_SINK3(n)

DP_SINK3(p)

DP_SINK2(n)

DP_SINK2(p)

DP_SINK1(n)

DP_SINK1(p)

DP_SINK0(n)

DP_SINK0(p)

I2C_SDA

TMDS_SINK2(p)

TMDS_SINK2(n)

TMDS_SINK1(p)

TMDS_SINK1(n)

TMDS_SINK0(p)

TMDS_SINK0(n)

TMDS_SINKCLK(p)

TMDS_SINKCLK(n)

GND

CAD_SINK

DP_HPD_SINK

CAD

VDD

*

1

HPD

AUX(p)_I

2

C(SCL)

AUX(n)_I

2

C(SDA)

VDD

Priority

TMDS_HPD_SINK

I

2

C_EN

LP

I

2

C_SCL

DPVadj

VDD

ML_IN0(p)

ML_IN0(n)

GND

ML_IN1(p)

ML_IN1(n)

VDD

ML_IN2(p)

ML_IN2(n)

GND

ML_IN3(p)

ML_IN3(n)

VCC

SN75DP122

SN75DP122

SLLS892 – FEBRUARY 2008

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SN75DP122

SLLS892 – FEBRUARY 2008

TERMINAL FUNCTIONS

TERMINAL

I/O DESCRIPTION

NAME NO.

MAIN LINK INPUT PINS

ML_IN 0 3, 4 I DisplayPort main link channel 0 differential input
ML_IN 1 6, 7 I DisplayPort main link channel 1 differential input
ML_IN 2 9, 10 I DisplayPort main link channel 2 differential input
ML_IN 3 12, 13 I DisplayPort main link channel 3 differential input

MAIN LINK PORT A OUTPUT PINS

DP_SINK 0 56, 55 O DisplayPort main link port a channel 0 differential output
DP_SINK 1 53, 52 O DisplayPort main link port a channel 1 differential output
DP_SINK 2 50, 49 O DisplayPort main link port a channel 2 differential output
DP_SINK 3 47, 46 O DisplayPort main link port a channel 3 differential output

MAIN LINK PORT B OUTPUT PINS

TMDS_SINK 2 25, 24 O TMDS data 2 differential output
TMDS_SINK 1 22, 21 O TMDS data 1 differential output
TMDS_SINK 0 19, 18 O TMDS data 0 differential output
TMDS_SINK CLK 16, 15 O TMDS data clock differential output

HOT PLUG DETECT PINS

HPD 37 O Hot plug detect output to the displayport source
DP_HPD_SINK 40 I DisplayPort port hot plug detect input
TMDS_HPD_SINK 32 I TMDS port hot plug detect input

AUXILIARY DATA PINS

AUX_I

2

C 36, 35 I/O Source side bidirectional displayport auxiliary data line
AUX_SINK 45, 43 I/O DisplayPort port bidirectional displayport auxiliary data line
I2C_SCL 29,

I/O TMDS port bidirectional ddc data lines

I2C_SDA 28

CABLE ADAPTER DETECT PINS

CAD 39 O Cable adapter detect output to the displayport source
CAD_SINK 41 I DisplayPort cable adapter detect input

CONTROL PINS

LP 30 I Low power select bar
Priority 33 I Output port priority selection
DPVadj 1 I DisplayPort main link output gain adjustment
VSadj 26 I TMDS compliant voltage swing control
I2C_EN 31 I Internal I2C register enable, used for HDMI / DVI connector differentiation

SUPPLY and GROUND PINS

VDD 2, 8, 34, 48, 54 5-V supply
VDD

*1

38 HPD/CAD supply
VCC 14, 17, 23 3.3-V supply
GND 5, 11, 20, 27, 42, 44, 51 Ground

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ABSOLUTE MAXIMUM RATINGS

SN75DP122

SLLS892 – FEBRUARY 2008

Table 1. Control Pin Lookup Table

SIGNAL LEVEL

(1)

STATE DESCRIPTION

H Normal Mode Normal operational mode for device

LP

Device is forced into a low power state causing the outputs to go to a high impedance

L Low Power Mode

state. All other inputs are ignored

H TMDS Port has

If both DP_HPD_SINK and TMDS_HPD_SINK are high, the TMDS port is selected

Priority

Priority

L DP Port has Priority If both DP_HPD_SINK and TMDS_HPD_SINK are high, the DP port is selected

The Internal I2C register is active and readable when the TMDS port is selected

H HDMI

indicating that the connector being used is HDMI

I2C_EN

The Internal I2C register is disabled and not readable when the TMDS port is selected

L DVI

indicating that the connector being used is DVI

4.53 k Ω Increased Gain Main link displayport output has an increased voltage swing

DP

Vadj

6.49 k Ω Nominal Gain Main link displayport output has a nominal voltage swing
10 k Ω Decreased Gain Main link displayport output has a decreased voltage swing

Compliant Voltage

VS

adj

5.11 k Ω Driver output voltage swing precision control to aid with system compliance

Swing

(1) (H) Logic High; (L) Logic Low

Explanation of the internal switching logic of the SN75DP122 is located in the application section at the end of
this data sheet.

ORDERING INFORMATION

(1)

PART NUMBER PART MARKING PACKAGE

SN75DP122RTQR 75DP122 56-pin QFN Reel (large)
SN75DP122RTQT 75DP122 56-pin QFN Reel (small)

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com .

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE UNIT

Supply voltage range

(2)

VDD, V

DD

*1

– 0.3 to 5.25 V

Supply voltage range V

CC

– 0.3 to 3.6 V
Main Link I/O (ML_IN x, DP_SINK x) Differential Voltage 1.5 V
TMDS I/O – 0.3 to 4 V

Voltage range HPD and CAD I/O – 0.3 to 5.25 V

Auxiliary I/O – 0.3 to 5.25 V
Control I/O – 0.3 to 5.25 V

Auxiliary and I2C I/O ± 8000

Human body model

(3)

V

All other pins ± 12000

Electrostatic discharge

Charged-device model

(3)

± 1000 V

Machine model

(4)

± 200 V

Continuous power dissipation See Dissipation Rating Table

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B
(4) Tested in accordance with JEDEC Standard 22, Test Method A115-A

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DISSIPATION RATINGS

THERMAL CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

SN75DP122

SLLS892 – FEBRUARY 2008

PCB JEDEC DERATING FACTOR

(1)

TA= 85 ° C

PACKAGE TA< 25 ° C

STANDARD

ABOVE TA= 25 ° C POWER RATING

Low-K 3623 mW 36.23 mW/ ° C 1449 mW

56-Pin QFN (RTQ)

High-K 1109 mW 11.03 mW/ ° C 443.9 mW

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX

(1)

UNIT

Junction-to-board thermal

R

θ JB

4x4 Thermal vias under powerpad 11.03 ° C/W

resistance
Junction-to-case thermal

R

θ JC

20.4 C/W

resistance

LP = 5 V, ML: VID= 600 mV, 2.7 Gbps PRBS;

Device power dissipation

P

D(1)

AUX: VID= 500 mV, 1 Mbps PRBS; 250 305 mW

DisplayPort selected

HPD/CAD = 5 V; V

DD

*1

= V

DD

LP = 5 V, ML: VID= 500 mV, 2.5 Gbps PRBS;

Device power dissipation TMDS

P

D(2)

270 420 mW

I2C: VID= 3.3 V, 100 Kbps PRBS; HPD/CAD = 5

selected

V; V

DD

*1

= V

DD

LP = 0 V, ML: VID= 600 mV, 2.7 Gbps PRBS;

Device power dissipation under

P

SD

75 85 µ W

AUX: VID= 500 mV, 1 Mbps PRBS; HPD/CAD =

low power

5 V; V

DD

*1

= V

DD

(1) The maximum rating is simulated under 5.25 V VDD.

MIN NOM MAX UNIT

V

DD

Supply voltage 4.5 5 5.25 V

V

DD

*1

HPD and CAD output reference voltage 1.62 5.25 V

V

CC

Supply voltage 3 3.3 3.6 V

T

A

Operating free-air temperature 0 85 ° C

MAIN LINK DIFFERENTIAL PINS

V

ID

Peak-to-peak input differential voltage 0.15 1.40 V

d

R

Data rate 2.7 Gbps

R

t

Termination resistance 45 50 55 Ω

V

Oterm

Output termination voltage 0 2 V

TMDS DIFFERENTIAL OUTPUT PINS

AV

CC

TMDS output termination voltage 3 3.3 3.6 V

d

R

Data rate 2.5 Gbps

R

t

Termination resistance 45 50 55 Ω

AUXILIARY AND I2C PINS

V

I

Input voltage 0 5.25 V

d

R(AUX)

Auxiliary data rate 1 MHz

d

R(I2C)

I2C data rate 100 kHz

HPD, CAD, AND CONTROL PINS

V

IH

High-level input voltage 2 5.25 V

V

IL

Low-level input voltage 0 0.8 V

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DEVICE POWER

ELECTRICAL CHARACTERISTICS

HOT PLUG AND CABLE ADAPTER DETECT

ELECTRICAL CHARACTERISTICS

SWITCHING CHARACTERISTICS

SN75DP122

SLLS892 – FEBRUARY 2008

The SN75DP122 is designed to operate off of two supply voltages. The DisplayPort port and the digital logic run
off of the 5V supply voltage. The TMDS level translator is powered off of the 3.3V supply.

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

DD

LP = 5 V, V

DD

*1

= VDD, Priority = 0 V 60 65

ML: VID= 600 mV, 2.7 Gbps PRBS

Supply current mA

AUX: VID= 500 mV, 1 Mbps PRBS

I

CC

0.1 0.25

DP/TMDS_HPD_SINK and CAD_SINK = 5 V

I

DD(2)

LP = 5 V, V

DD

*1

= VDD, Priority = 1 V 2 4

ML: VID= 500 mV, 2.5 Gbps PRBS

Supply current mA

AUX: VI= 2 V, 100 kHz

I

CC(2)

80 110

DP/TMDS_HPD_SINK and CAD_SINK = 5 V

I

DD

*1

Supply current V

DD

*1

= 5.25 V 0.1 4 mA

I

SD

Shutdown current LP = 0 V 1 16 µ A

The SN75DP122 is designed to support the switching of the Hot Plug Detect and Cable adapter Detect signals.
The SN75DP122 has a built in level shifter for the HPD and CAD outputs. The output voltage level of the HPD
and CAD pins is defined by the voltage level of the V

DD

*1

pin.

When the DisplayPort port is selected, the state of CAD_SINK is propagated to the CAD output pin. If the TMDS
port is selected, the CAD output pin stays HIGH as long as that port is selected.

Explanation of HPD and the internal logic of the SN75DP128 is located in the application section at the end of
the data sheet.

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH5

High-level output voltage IOH= – 100 µ A, V

DD

*1

= 5 V 4.5 5 V

V

OH3.3

High-level output voltage IOH= – 100 µ A, V

DD

*1

= 3.3 V 3 3.3 V

V

OH2.5

High-level output voltage IOH= – 100 µ A, V

DD

*1

= 2.5 V 2.25 2.5 V

V

OH1.8

High-level output voltage IOH= – 100 µ A, V

DD

*1

= 1.8 V 1.62 1.8 V

V

OL

Low-level output voltage IOH= 100 µ A, 0 0.4 V

I

H

High-level input current VIH= 2.0 V, V

DD

= 5.25 V – 10 10 µ A

I

L

Low-level input current VIL= 0.8 V, V

DD

= 5.25 V – 10 10 µ A

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

PD(CAD)

Propagation delay V

DD

*1

= 5 V 5 30 ns

t

PD(HPD)

Propagation delay V

DD

*1

= 5 V 30 110 ns

t

T1(HPD)

HPD logic switch pause time V

DD

*1

= 5 V 2 4.7 ms

t

T2(HPD)

HPD logic switch time V

DD

*1

= 5 V 170 400 ms

t

M(HPD)

Minimum output pulse duration V

DD

*1

= 5 V 100 ns

t

Z(HPD)

Low power to high-level propagation delay V

DD

*1

= 5 V 30 50 110 ns

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HPDInput

100kW

100kW

HPDOutput

DP122

SinkHotPlugDetect

PulseDuration

Minimum

HotPlugDetect

OutputPulseDuration

HPD

0V

V

DD

HPD_B

HPD_A

50%

t

PD(HPD)

V

DD

*1

0V

0V

50%

t

m(HPD)

SN75DP122

SLLS892 – FEBRUARY 2008

Figure 1. HPD Test Circuit

Figure 2. HPD Timing Diagram #1

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SinkHotPlugDetect

Timeout

PortB

Selected

Port A

Selected

HPD

Priority

HPD_A &HPD_B

V

DD

V

DD

50%

0V

V

DD

*1

t

1(HPD)

50%

t

2(HPD)

0V

HPD

0V

V

DD

0V

0V

V

DD

*1

50%

t

Z(HPD)

50%

HPD_B

HPD_A

SN75DP122

SLLS892 – FEBRUARY 2008

Figure 3. HPD Timing Diagram #2

Figure 4. HPD Timing Diagram #3

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DisplayPort Auxiliary Pins

ELECTRICAL CHARACTERISTICS

SWITCHING CHARACTERISTICS

3.3V

10 pF

0.5 pF

AUX+

AUX-

50 W 50 W

100 W

SN75DP122

CAD=0

AUX
+ or -

3.3 V3.3 V

10 pF 50 pF

2kW

100kW

SN75DP122

CAD=1

SN75DP122

SLLS892 – FEBRUARY 2008

The SN75DP122 is designed to support the bidirectional auxiliary signals through the DisplayPort port in both a
differential (DisplayPort) mode and an I2C (DVI, HDMI) mode. The performance of the Auxiliary bus is optimized
based on the status of the CAD_SINK pin.

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

Pass1

Maximum passthrough voltage (CAD=1) V

DD

= 4.5 V, VI= 5 V, IO= 100 µ A 2.4 3.6 V

I

OZ

Output current from unselected output V

DD

= 5.25 V, VO= 0 V to 3.6 V, VI= 0 V – 5 5 µ A

DC bias = 1 V, AC = 1.4 V

p-p

, F = 100 kHz,

C

IO(off)

I/O capacitance when in low power 9 12 pF

CAD = High
DC bias = 1 V, AC = 1.4 V

p-p

, F = 100 kHz,

C

IO(on)

I/O capacitance when in normal operation 18 25 pF

CAD = Low

r

ON(C0)

On resistance V

DD

= 4.5 V, VI= 0 V or 3.6 V, IO= 5 mA, CAD = Low 5 10 Ω

Δ r

ON

On resistance V

DD

= 4.5 V, VI= 0 V or 2 V, IO= 5 mA, CAD = Low 1 5 Ω

V

DD

= 4.5 V, VI= 0 V or 3.6 V, IO= 5 mA, CAD =

r

ON(C1)

On resistance 10 18 Ω

High

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

sk(AUX)

Intra-pair skew VID= 400 mV, VIC= 2 V 40 80 ps

I

L(AUX)

Single Line Insertion Loss VID= 500 mV, VIC= 2 V, F = 1 MHz, CAD = Low 0.4 dB

t

PLH(AUXC0)

Propagation delay time, low to high CAD = Low, F = 1 MHz 3 ns

t

PHL(AUXC0)

Propagation delay time, high to low CAD = Low, F = 1 MHz 3 ns

t

PLH(AUXC1)

Propagation delay time, low to high CAD = High, F = 100 kHz 3 ns

t

PHL(AUXC1)

Propagation delay time, high to low CAD = High, F = 100 kHz 3 ns

Figure 5. Auxiliary Channel Test Circuit (CAD = LOW)

Figure 6. Auxiliary Channel Test Circuit (CAD = HIGH)

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50%

2.2V

1.8V

T

sk(AUX)

Differential
AUXInput

Differential

AUXOutput

AUXInput

2.2V

1.8V

0V

0V

t

PHL(AUXCO)

t

PLH(AUXCO)

AUX

Input

+ or -

AUX

Output

+ or -

2V

1V

1V

0V

2V

0V

t

PHL(AUXC1)

t

PLH(AUXC1)

DisplayPort Link Pins

SN75DP122

SLLS892 – FEBRUARY 2008

Figure 7. Auxiliary Channel Skew Measurement

Figure 8. Auxiliary Channel Delay Measurement (CAD = LOW)

Figure 9. Auxiliary Channel Delay Measurement (CAD = HIGH)

The SN75DP122 is designed to support DisplayPort ’ s high speed differential main link through the DisplayPort
port. The main link I/O of the SN75DP122 are designed to track the magnitude and frequency characteristics of
the input waveform and replicate them on the output. A feature has also been incorporated in the SN75DP122 to
increase the either increase of decrease the output amplitude via the resistor connected between the DPVADJ
pin and ground.

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