Texas Instruments SN75C1406NS, SN75C1406D, SN75C1406DR, SN75C1406DW, SN75C1406DWR Datasheet

SN75C1406

TRIPLE LOW-POWER DRIVERS/RECEIVERS

SLLS148D – MAY 1990 – REVISED DECEMBER 1999

D

Meet or Exceed the Requirements of
TIA/EIA-232-F and ITU Recommendation

D, DW, N, OR NS PACKAGE

(TOP VIEW)

V.28

D

Very Low Power Consumption . . .
5 mW Typ

D

Wide Driver Supply Voltage Range . . .
±4.5 V to ±15 V

D

Driver Output Slew Rate Limited to
30 V/µs Max

D

Receiver Input Hysteresis . . . 1000 mV Typ

D

Push-Pull Receiver Outputs

D

On-Chip Receiver 1-µs Noise Filter

D

Functionally Interchangeable With Motorola

V

DD

1RA
1DY
2RA
2DY
3RA
3DY

V

SS

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

V

CC

1RY
1DA
2RY
2DA
3RY
3DA

9

GND

MC145406 and Texas Instruments
TL145406

D

Package Options Include Plastic
Small-Outline (D, DW, NS) Packages and
(N) DIPs

description

The SN75C1406 is a low-power BiMOS device containing three independent drivers and receivers that are used
to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). This device is
designed to conform to TIA/EIA-232-F . The drivers and receivers of the SN75C1406 are similar to those of the
SN75C188 quadruple driver and SN75C189A quadruple receiver, respectively. The drivers have a controlled
output slew rate that is limited to a maximum of 30 V/µs, and the receivers have filters that reject input noise
pulses shorter than 1 µs. Both these features eliminate the need for external components.

The SN75C1406 is designed using low-power techniques in a BiMOS technology. In most applications, the
receivers contained in these devices interface to single inputs of peripheral devices such as ACEs, UARTs, or
microprocessors. By using sampling, such peripheral devices are usually insensitive to the transition times of
the input signals. If this is not the case, or for other uses, it is recommended that the SN75C1406 receiver outputs
be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families.

The SN75C1406 is characterized for operation from 0°C to 70°C.

logic symbol

1RA
2RA
3RA
1DY

2DY
3DY

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.

†

2
4
6
3

5
7

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

15
13
11
14

12
10

1RY
2RY
3RY
1DA

2DA
3DA

logic diagram, each driver and receiver

RA

DY

RY

DA

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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Copyright  1999, Texas Instruments Incorporated

1

SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS

SLLS148D – MAY 1990 – REVISED DECEMBER 1999

schematics of inputs and outputs

Input

DA

EQUIVALENT DRIVER INPUT

V

DD

Internal

1.4-V Reference

V

SS

GND

EQUIVALENT RECEIVER INPUT EQUIVALENT RECEIVER OUTPUT

EQUIVALENT DRIVER OUTPUT

74 Ω

72 Ω

160 Ω

V

DD

Output
DY

V

SS

V

CC

Input

RA

ESD

Protection

GND

All resistor values shown are nominal.

3.4 kΩ

ESD

Protection

1.5 kΩ

530 Ω

Output
RY

GND

2

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SN75C1406

Input voltage, V

V

TRIPLE LOW-POWER DRIVERS/RECEIVERS

SLLS148D – MAY 1990 – REVISED DECEMBER 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

Supply voltage, VSS –15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI: Driver VSS to V
Output voltage range, V

Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltages are with respect to the network ground terminal.

2. The package thermal impedance is calculated in accordance with JESD 51.

(see Note 1) 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver –30 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

: Driver (VSS – 6 V) to (VDD + 6 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

Receiver –0.3 V to (VCC + 0.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 57°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V
Supply voltage, V
Supply voltage, V

p

High-level input voltage, V
Low-level input voltage, V
High-level output current, I
Low-level output current, I
Operating free-air temperature, T

DD
SS
CC

I

IH

IL

OH

OL

Driver VSS+2 V
Receiver ±25

A

4.5 12 15 V

–4.5 –12 –15 V

4.5 5 6 V
DD

2 V

0.8 V

–1 mA

3.2 mA

0 70 °C

†

DD

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3

SN75C1406

VOHHigh-level output voltage

IH

,

V

V

g

IH

,

V

IDDSupply current from V

,

A

ISSSupply current from V

,

A

L

,

L

,

TRIPLE LOW-POWER DRIVERS/RECEIVERS

SLLS148D – MAY 1990 – REVISED DECEMBER 1999

DRIVER SECTION

electrical characteristics over operating free-air temperature range, V

= 5 V ± 10% (unless otherwise noted)

V

CC

PARAMETER TEST CONDITIONS MIN

V

p

OL

I

IH

I

IL

I

OS(H)

I

OS(L)

r

O

†

All typical values are at TA = 25°C.

‡

Not more than one output should be shorted at a time.

NOTES: 3. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic

Low-level output voltage V
(see Note 3)

High-level input current VI = 5 V, See Figure 2 1 µA
Low-level input current VI = 0, See Figure 2 –1
High-level short-circuit

output current
Low-level short-circuit

output current

pp

pp

Output resistance

levels only.

4. Test conditions are those specified by TIA/EIA-232-F.

‡

‡

DD

SS

= 0.8 V,

See Figure 1

= 2 V,

See Figure 1

VI = 0.8 V, VO = 0 or VSS, See Figure 1 –7.5 –12 –19.5 mA

VI = 2 V, VO = 0 or VDD, See Figure 1 7.5 12 19.5 mA

No load,
All inputs at 2 V or 0.8 V

No load,
All inputs at 2 V or 0.8 V

VDD = VSS = VCC = 0,
See Note 4

RL = 3 kΩ,

RL = 3 kΩ,

VDD = 5 V, VSS = –5 V 4 4.5
VDD = 12 V, VSS = –12 V 10 10.8
VDD = 5 V, VSS = –5 V –4.4 –4
VDD = 12 V, VSS = –12 V –10.7 –10

VDD = 5 V, VSS = –5 V 115 250
VDD = 12 V, VSS = –12 V 115 250
VDD = 5 V, VSS = –5 V –115 –250
VDD = 12 V, VSS = –12 V –115 –250
VO = –2 V to 2 V,

= 12 V, VSS = – 12 V,

DD

†

TYP

300 400 Ω

MAX UNIT

µ

µ

switching characteristics at TA = 25°C, VDD = 12 V, VSS = –12 V, VCC = 5 V ± 10%

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

Propagation delay time, low- to high-level output

PLH

t

Propagation delay time, high- to low-level output

PHL

t

Transition time, low- to high-level output

TLH

t

Transition time, high- to low-level output

THL

t

Transition time, low- to high-level output

TLH

t

Transition time, high- to low-level output

THL

SR Output slew rate

§

t

and t

PHL

¶

Measured between 10% and 90% points of output waveform

#

Measured between 3-V and –3-V points of output waveform (TIA/EIA-232-F conditions) with all unused inputs tied either high or low

include the additional time due to on-chip slew rate and are measured at the 50% points.

PLH

§

§

R

¶
¶

#

#

= 3 kΩ to 7 kΩ,C

See Figure 3

RL = 3 kΩ to 7 kΩ,CL = 2500 pF,
See Figure 3

RL = 3 kΩ to 7 kΩ,CL = 2500 pF,
See Figure 3

RL = 3 kΩ to 7 kΩ,CL = 15 pF,
See Figure 3

= 15 pF,

0.53 2 3.2 µs

0.53 2 3.2 µs

1.2 3 µs

2.5 3.5 µs

1 2 µs

1 2 µs

4 10 30 V/µs

4

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TRIPLE LOW-POWER DRIVERS/RECEIVERS

VOHHigh-level output voltage

V

See Figure 5

IIHHigh-level input current

mA

IILLow-level input current

I

g

V

V

See Figure 4

8–15

mA

I

V

V

V

V

See Figure 4

1325mA

ICCSupply current from V

A

L

,

L

,

RECEIVER SECTION

SN75C1406

SLLS148D – MAY 1990 – REVISED DECEMBER 1999

electrical characteristics over operating free-air temperature range, V
V

= 5 V ± 10% (unless otherwise noted)

CC

PARAMETER TEST CONDITIONS MIN

V

IT+

V

IT–

V

hys

V

OL

OS(H)

OS(L)

†

All typical values are at TA = 25°C.

NOTE 5: If the inputs are left unconnected, the receiver interprets this as an input low and the receiver outputs remain in the high state.

Positive-going input
threshold voltage

Negative-going input
threshold voltage

Input hysteresis voltage
(V

IT+–VIT–

Low-level output voltage VI = 3 V, IOL = 3.2 mA, See Figure 5 0.17 0.4 V

High-level short-circuit
output current

Low-level short-circuit
output current

pp

)

p

p

p

See Figure 5 1.7 2 2.55 V

See Figure 5 0.65 1 1.25 V

VI = 0.75 V, IOH = –20 µA, See Figure 5 and Note 5 3.5

VI = 0.75 V,

VI = 2.5 V 3.6 4.6 8.3
VI = 3 V 0.43 0.55 1
VI = –2.5 V –3.6 –5 –8.3
VI = –3 V –0.43 –0.55 –1

= 0.75 V,

I

=

I

CC

No load,

CC

All inputs at 0 or 5 V

,

IOH = –1 mA,

= 0,

O

=

O

CC

VCC = 4.5 V 2.8 4.4
VCC = 5 V
VCC = 5.5 V 4.3 5.4

,

VDD = 5 V, VSS = –5 V 320 450
VDD = 12 V, VSS = –12 V 320 450

= 12 V, VSS = –12 V,

DD

†

TYP

600 1000 mV

3.8 4.9

–

MAX UNIT

µ

switching characteristics at TA = 25°C, VDD = 12 V , VSS = –12 V , VCC = 5 V ± 10% (unless otherwise
noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

Propagation delay time, low- to high-level output 3 4 µs

PLH

t

Propagation delay time, high- to low-level output

PHL

t

Transition time, low- to high-level output

TLH

t

Transition time, high- to low-level output

THL

t

Duration of longest pulse rejected as noise

w(N)

‡

Measured between 10% and 90% points of output waveform

§

The receiver ignores any positive- or negative-going pulse that is less than the minimum value of t
pulse greater than the maximum of t

w(N)

‡
‡

§

.

C

= 50 pF, R

See Figure 6

CL = 50 pF, RL = 5 kΩ 1 4 µs

= 5 kΩ,

) and accepts any positive- or negative-going

w(N

3 4 µs
300 450 ns
100 300 ns

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5

SN75C1406

)

)

TRIPLE LOW-POWER DRIVERS/RECEIVERS

SLLS148D – MAY 1990 – REVISED DECEMBER 1999

PARAMETER MEASUREMENT INFORMATION

I

V

DD

V

CC

V

I

V

O

V

SS

Figure 1. Driver Test Circuit

VOH, VOL, I

OS(L

OS(L)

–I

OS(H)

RL = 3 kΩ

, I

OS(H

VDD or GND

VSS or GND

V

DD

I

IH

V

I

–I

IL

V

I

V

CC

V

SS

Figure 2. Driver Test Circuit, IIL, I

IH

V

DD

Input

Pulse

Generator

(See Note B)

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns.

V

CC

R

L

V

SS

TEST CIRCUIT

C

L

(see Note A)

Figure 3. Driver Test Circuit and Voltage Waveforms

V

DD

V

CC

V

I

V

SS

–I

OS(H)

I

OS(L)

V

CC

Input

Output

VIT, V

3 V

1.5

t

PHL

90%

t

THL

V

DD

V

CC

I

V

SS

50%

10%

VOLTAGE WAVEFORMS

V

OL

1.5

I

OL

50%

10%

0 V

t

PLH

V

t

TLH

–I

V

OH

OH

OL

90%

V

OH

Figure 4. Receiver Test Circuit, I

6

, I

OS(H)

OS(L)

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Figure 5. Receiver Test Circuit, VIT, VOL, V

OH

TRIPLE LOW-POWER DRIVERS/RECEIVERS

SLLS148D – MAY 1990 – REVISED DECEMBER 1999

PARAMETER MEASUREMENT INFORMATION

SN75C1406

V

DD

Input

Pulse

Generator

(See Note B)

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns.

V

CC

R

L

V

SS

TEST CIRCUIT

C

L

(see Note A)

Input

Output

t

PHL

t

THL

50%

90%

50%

50%

10%

VOLTAGE WAVEFORMS

10%

50%

t

PLH

90%

t

Figure 6. Receiver Test Circuit and Voltage Waveforms

APPLICATION INFORMATION

The TIA/EIA-232-F specification is for data interchange between a host computer and a peripheral at signaling
rates up to 20 kbit/s. Many TIA/EIA-232-F devices will operate at higher data rates with lower capacitive loads
(short cables). For reliable operation at greater than 20 kbit/s, the designer needs to have control of both ends
of the cable. By mixing different types of TIA/EIA-232-F devices and cable lengths, errors can occur at higher
frequencies (above 20 kbit/s). When operating within the TIA/EIA-232-F requirements of less than 20 kbit/s and
with compliant line circuits, interoperability is assured. For applications operating above 20 kbit/s, the design
engineer should consider devices and system designs that meet the TIA/EIA-232-F requirements.

TLH

4 V

0 V

V

V

OH

OL

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7

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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright  1999, Texas Instruments Incorporated