SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151C – DECEMBER 1988 – REVISED MARCH 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Meets or Exceeds the Requirements of
ANSI EIA/TIA-232-E and ITU
Recommendation V.28
D
Very Low Power Consumption
5 mW Typ
D
Wide Driver Supply Voltage . . . ±4.5 V
to ±15 V
D
Driver Output Slew Rate Limited to
30 V/µs Max
D
Receiver Input Hysteresis...1000 mV Typ
D
Push-Pull Receiver Outputs
D
On-Chip Receiver 1-µs Noise Filter
D
Functionally interchangeable With Motorola
MC145404
description
The SN75C1 154 is a low-power BiMOS device containing four independent drivers and receivers that are used
to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). This device has been
designed to conform to ANSI EIA/TIA-232-E. The drivers and receivers of the SN75C1 154 are similar to those
of the SN75C188 quadruple driver and SN75C189A quadruple receiver, respectively. The drivers have a
controlled output slew rate that is limited to a maximum of 30 V/µs and the receivers have filters that reject input
noise pulses of shorter than 1 µs. Both these features eliminate the need for external components.
The SN75C1154 is designed using low-power techniques in a BiMOS technology. In most applications, the
receivers contained in these devices interface to single inputs of peripheral devices such as ACEs, UARTs, or
microprocessors. By using sampling, such peripheral devices are usually insensitive to the transition times of
the input signals. If this is not the case or for other uses, it is recommended that the SN75C1 154 receiver outputs
be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families.
The SN75C1154 is characterized for operation from 0°C to 70°C.
logic symbol
†
4DY
3DY
2DY
1DY
4RA
3RA
2RA
1RA
4DA
3DA
2DA
1DA
4RY
3RY
2RY
1RY
9
7
5
3
8
6
4
2
12
14
16
18
13
15
17
19
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
logic diagram (positive logic)
typical of each driver
typical of each receiver
DY
RA
DA
RY
3, 5, 7, 9
2, 4, 6, 8
18, 16, 14, 12
19, 17, 15, 13
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
V
DD
1RA
1DY
2RA
2DY
3RA
3DY
4RA
4DY
V
SS
V
CC
1RY
1DA
2RY
2DA
3RY
3DA
4RY
4DA
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DW OR N PACKAGE
(TOP VIEW)
SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151C – DECEMBER 1988 – REVISED MARCH 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
1.5 kΩ
V
DD
EQUIVALENT DRIVER INPUT
Internal
1.4-V Reference
V
SS
GND
Input
DA
V
SS
V
DD
Output
DY
160 Ω
74 Ω
72 Ω
RA
Input
GND
530 Ω
3.4 kΩ
ESD
Protection
ESD
Protection
Output
RY
GND
V
CC
EQUIVALENT DRIVER OUTPUT
EQUIVALENT RECEIVER INPUT EQUIVALENT RECEIVER OUTPUT
Resistor values shown are nominal.
SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151C – DECEMBER 1988 – REVISED MARCH 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
DD
(see Note 1) 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage, V
SS
–15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
: Driver VSS to V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver –30 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
: Driver (VSS –6 V) to (VDD + 6 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver –0.3 V to (V
CC
+ 0.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN75C1 154 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to the network GND terminal.
DISSIPATION RATING TABLE
TA ≤ 25°C DERATING FACTOR TA = 70°C
PACKAGE
A
POWER RATING ABOVE TA = 25°CAPOWER RATING
DW 1125 mW 9.0 mW/°C 720 mW
N 1150 mW 9.2 mW/°C 736 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
DD
4.5 12 15 V
Supply voltage, V
SS
–4.5 –12 –15 V
Supply voltage, V
CC
4.5 5 6 V
p
Driver VSS+2 V
DD
Input voltage, V
I
Receiver ±25
V
High-level input voltage, V
IH
2
Low-level input voltage, V
IL
Driver
0.8
V
High-level output current, I
OH
–1 mA
High-level output current, I
OL
Receiver
3.2 mA
Operating free-air temperature, T
A
0 70 °C
SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151C – DECEMBER 1988 – REVISED MARCH 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DRIVER SECTION
electrical characteristics over operating free-air temperature range, V
DD
= 12 V, VSS = –12 V,
V
CC
= 5 V ±10% (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
p
V
= 0.8 V, R
= 3 kΩ,
VDD = 5 V, VSS = –5 V 4 4.5
VOHHigh-level output voltage
IL
,
See Figure 1
L
,
VDD = 12 V, VSS = –12 V 10 10.8
V
Low-level output voltage V
= 2 V, R
= 3 kΩ,
VDD = 5 V, VSS = –5 V –4.4 –4
V
OL
g
(see Note 2)
IH
,
See Figure 1
L
,
VDD = 12 V, VSS = –12 V –10.7 –10
V
I
IH
High-level input current VI = 5 V, See Figure 2 1 µA
I
IL
Low-level input current VI = 0, See Figure 2 –1 µA
High-level short circuit
I
OS(H)
g
output current
‡
V
I
=
0.8 V
,
V
O
=
0 or V
SS
,
See Figure 1
–7.5–12–19.
5
mA
Low-level short circuit
I
OS(L)
output current
‡
V
I
= 2 V,
V
O
= 0 or
V
DD
,
See Figure 1
7.51219.5
mA
pp
p
VDD = 5 V, VSS = –5 V 115 250
IDDSupply current from V
DD
No load, All inputs at 2 V or 0.8 V
VDD = 12 V VSS = –12 V 115 250
µ
A
pp
p
VDD = 5 V, VSS = –5 V –115 –250
ISSSupply current from V
SS
No load, All inputs at 2 V or 0.8 V
VDD = 12 V VSS = –12 V –115 –250
µ
A
r
o
Output resistance VDD = VSS = VCC = 0, VO = –2 V to 2 V, See Note 3 300 400 Ω
†
All typical values are at TA = 25°C.
‡
Not more than one output should be shorted at one time.
NOTES: 2. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only.
3. Test conditions are those specified by EIA/TIA-232-E.
switching characteristics, VDD = 12 V, VSS = –12 V, VCC = 5 V ±10%, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low- to high-level
output
§
1.2 3 µs
t
PHL
Propagation delay time, high- to low-level
output
§
RL = 3 to 7 kΩ, CL = 15 pF, See Figure 3
2.5 3.5 µs
t
TLH
Transition time, low- to high-level output
¶
0.53 2 3.2 µs
t
THL
Transition time, high- to low-level output
¶
0.53 2 3.2 µs
t
TLH
Transition time, low- to high-level output
#
RL = 3 to 7 kΩ, CL = 2500 pF, See Figure 3 1 2 µs
t
THL
Transition time, high- to low-level output
#
RL = 3 to 7 kΩ, CL = 2500 pF, See Figure 3 1 2 µs
SR Output slew rate RL = 3 to 7 kΩ, CL = 15 pF, See Figure 3 4 10 30 V/µs
§
t
PHL
and t
PLH
include the additional time due to on-chip slew rate control and are measured at the 50% points.
¶
Measured between 10% and 90% points of output waveform.
#
Measured between 3 V and –3 V points of output waveform (EIA/TIA-232-E conditions) with all unused inputs tied either high or low.
SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151C – DECEMBER 1988 – REVISED MARCH 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RECEIVER SECTION
electrical characteristics over operating free-air temperature range, V
DD
= 12 V , VSS = –12 V , V
CC
= 5 V ± 10% (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
Positive-going input
V
IT+
gg
threshold voltage
See Figure 5
1.7
2.1
2.55
V
Negative-going input
V
IT–
ggg
threshold voltage
See Figure 5
0.6511.25
V
V
hys
Input hysteresis voltage
(V
IT+
– V
IT–
)
600 1000 mV
VI = 0.75 V , IOH = –20 µA, See Figure 5 and Note 4 3.5
p
VCC = 4.5 V 2.8 4.4
VOHHigh-level output voltage
VI = 0.75 V ,
IOH = –1 mA,
VCC = 5 V
3.8 4.9
V
See Figure 5
VCC = 5.5 V 4.3 5.4
V
OL
Low-level output voltage VI = 3 V, IOL = 3.2 mA, See Figure 5 0.17 0.4 V
p
VI = 25 V 3.6 4.6 8.3
IIHHigh-level input current
VI = 3 V 0.43 0.55 1
p
VI = –25 V –3.6 –5 –8.3
mA
IILLow-level input current
VI = –3 V –0.43 –0.55 –1
p
I
OS(H)
Short-circuit output at high level
V
I
= 0.75 V,
V
O
= 0,
See Figure 4
–
8–15
mA
p
I
OS(L)
Short-circuit output at low level
V
I
=
V
CC
,
V
O
=
V
CC
,
See Figure 4
1325mA
pp
No load,
VDD = 5 V, VSS = –5 V 400 600
ICCSupply current from V
CC
All inputs at 0 or 5 V
VDD = 12 V, VSS = –12 V 400 600
µ
A
†
All typical values are at TA = 25°C.
NOTE 4: If the inputs are left unconnected, the receiver interprets this as an input low and the receiver outputs will remain in the high state.
switching characteristics, VDD = 12 V, VSS = –12 V, VCC = 5 V ± 10%, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low- to high-level output 3 4 µs
t
PHL
Propagation delay time, high- to low-level output
p
3 4 µs
t
TLH
Transition time, low- to high-level output
C
L
= 50 pF,
R
L
= 5 kΩ,
See Figure 6
300 450 ns
t
THL
Transition time, high- to low-level output 100 300 ns
t
w(N)
Duration of longest pulse rejected as noise
‡
CL = 50 pF, RL = 5 kΩ 1 4 µs
‡
The receiver ignores any positive- or negative-going pulse that is less than the minimum value of t
w(N)
and accepts any positive- or negative-going
pulse greater than the maximum of t
w(N)
.
SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151C – DECEMBER 1988 – REVISED MARCH 1997
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver Test Circuit
V
OH
, VOL, I
OSL
, I
OSH
V
DD
V
CC
V
I
V
O
VSS or GND
VDD or GND
I
OSL
–I
OSH
V
SS
RL = 3 kΩ
Figure 2. Driver Test Circuit, IIL, I
IH
V
I
V
I
V
SS
V
DD
V
CC
I
IH
–I
IL
V
SS
R
L
V
CC
V
DD
C
L
(see Note B)
Pulse
(see Note A)
Generator
Input
Input
Output
1.5
50%
10%
90%
t
PLH
t
PHL
t
THL
t
TLH
V
O
H
V
O
L
3 V
0 V
50%
10%
90%
1.5
TEST CIRCUIT
VOLTAGE W AVEFORMS
NOTES: A. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns.
B. CL includes probe and jig capacitance.
Figure 3. Driver Test Circuit and Voltage Waveforms
Figure 4. Receiver Test Circuit, I
OSH
, I
OSL
V
DD
V
CC
V
I
V
SS
–I
OS(H)
I
OS(L)
V
CC
Figure 5. Receiver Test Circuit, VIT, VOL, V
OH
V
OL
V
OH
–I
OH
I
OL
V
SS
V
CC
V
DD
VIT, V
I
SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151C – DECEMBER 1988 – REVISED MARCH 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
SS
R
L
V
CC
V
DD
C
L
(see Note B)
Pulse
(see Note A)
Generator
Input
Input
Output
50%
50%
10%
90%
t
PLH
t
PHL
t
THL
t
TLH
V
OH
V
OL
4 V
0 V
50%
10%
90%
50%
TEST CIRCUIT
VOLTAGE W AVEFORMS
NOTES: A. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns.
B. CL includes probe and jig capacitance.
Figure 6. Receiver Test Circuit and Voltage Waveforms
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