Datasheet SN65ALS180D, SN65ALS180DR, SN65ALS180N, SN75ALS180N, SN75ALS180D Datasheet (Texas Instruments)

SN65ALS180, SN75ALS180

DIFFERENTIAL DRIVER AND RECEIVER PAIRS

SLLS052E – AUGUST 1987 – REVISED OCTOBER 1998

D

Meet or Exceed the Requirements of
TIA/EIA-422-B, TIA/EIA-485-A

†

and

ITU Recommendation V.11

D

High-Speed Advanced Low-Power Schottky
Circuitry

D

Designed for 25-MBaud Operation in Both
Serial and Parallel Applications

D

Low Skew Between Devices...6 ns Max

D

Low Supply-Current Requirements...
30 mA Max

D

Individual Driver and Receiver I/O Pins With
Dual V

D

Wide Positive and Negative Input/Output

and Dual GND

CC

Bus Voltage Ranges

D

Driver Output Capacity...±60 mA

D

Thermal Shutdown Protection

D

Driver Positive- and Negative-Current
Limiting

D

Receiver Input Impedance...12 kΩ Min

D

Receiver Input Sensitivity...±200 mV Max

D

Receiver Input Hysteresis...60 mV Typ

D

Operate From a Single 5-V Supply

D

Glitch-Free Power-Up and Power-Down
Protection

D OR N PACKAGE

(TOP VIEW)

NC

1

R

2

RE

3

DE

4

D

5

GND

6

GND

7

NC – No internal connection

14
13
12
11
10

V

CC

V

CC

A
B
Z
Y

9
8

NC

description

The SN65ALS180 and SN75ALS180 differential driver and receiver pairs are monolithic integrated
circuits designed for bidirectional data communication on multipoint bus-transmission lines. They are designed
for balanced transmission lines and meet TIA/EIA-422-B, TIA/EIA-485-A, and ITU Recommendation V.11.

The SN65ALS180 and SN75ALS180 combine a 3-state differential line driver and a differential input line
receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and
active-low enables, respectively, that can be externally connected together to function as a direction control.
The driver differential outputs and the receiver differential inputs are connected to separate terminals for greater
flexibility and are designed to offer minimum loading to the bus when the driver is disabled or V

These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for
party-line applications.

The SN65ALS180 is characterized for operation from –40°C to 85°C. The SN75ALS180 is characterized for
operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

†

These devices meet or exceed the requirements of TIA/EIA-485-A, except for the Generator Contention T est (para. 3.4.2) and the Generator

These devices meet or exceed the requirements of TIA/EIA-485-A, except for the Generator Contention T est (para. 3.4.2) and the Generator
Current Limit (para. 3.4.3). The applied test voltage ranges are –6 V to 8 V for the SN75ALS180 and –4.5 V to 8 V for the SN65ALS180.

Current Limit (para. 3.4.3). The applied test voltage ranges are –6 V to 8 V for the SN75ALS180 and –4.5 V to 8 V for the SN65ALS180.

CC

= 0.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

1

SN65ALS180, SN75ALS180
DIFFERENTIAL DRIVER AND RECEIVER PAIRS

SLLS052E – AUGUST 1987 – REVISED OCTOBER 1998

Function Tables

DRIVER

INPUT ENABLE

D DE

H H H L

L H L H
X L Z Z

RECEIVER

DIFFERENTIAL INPUTS

A–B RE R

VID ≥ 0.2 V L H

–0.2 V < VID < 0.2 V L ?

VID ≤ –0.2 V L L

X H Z

Open L H

H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)

OUTPUTS

Y Z

ENABLE OUTPUT

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

DE

RE

4
5

D

3
2

R

EN1

EN2

2

1
1

logic diagram (positive logic)

4

DE

5

D

3

RE

2

R

10

10

9

Y

10

Z

12

A

11

B

9

Y
Z

9

Y
Z

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

schematics of inputs and outputs

V

CC

R

(eq)

Input

SN65ALS180, SN75ALS180

DIFFERENTIAL DRIVER AND RECEIVER PAIRS

SLLS052E – AUGUST 1987 – REVISED OCTOBER 1998

RECEIVER A INPUTEQUIVALENT OF EACH INPUT RECEIVER B INPUT

18 kΩ

NOM

V

CC

3 kΩ
NOM

V

CC

Input

180 kΩ
NOM

18 kΩ

NOM

3 kΩ
NOM

Input

180 kΩ

NOM

Driver and Driver Enable Inputs: R
Receiver Enable Input: R
R

= Equivalent Resistor

(eq)

= 30 kΩ NOM

(eq)

DRIVER OUTPUT TYPICAL OF RECEIVER OUTPUT

= 12 kΩ NOM

(eq)

V

CC

Output

1.1 kΩ
NOM

85 Ω
NOM

V

CC

Output

1.1 kΩ
NOM

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3

SN65ALS180, SN75ALS180

Voltage at any bus terminal (separately or common mode), V

or V

V

High-level output current, I

Low-level output current, I

mA

Operating free-air temperature, T

°C

DIFFERENTIAL DRIVER AND RECEIVER PAIRS

SLLS052E – AUGUST 1987 – REVISED OCTOBER 1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

Voltage range at any bus terminal –10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Enable input voltage, V
Package thermal impedance, θ

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.

2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.

(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

st

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

High-level input voltage, V
Low-level input voltage, V
Differential input voltage, VID (see Note 3) ±12 V

p

NOTE 3: Dif ferential-input/output bus voltage is measured at the noninverting terminal, A/Y, with respect to the inverting terminal, B/Z.

CC

p

IH

IL

p

p

OH

OL

p

A

I

IC

D, DE, and RE 2 V
D, DE, and RE 0.8 V

Driver –60 mA
Receiver –400 µA
Driver 60
Receiver 8
SN65ALS180 –40 85
SN75ALS180 0 70

4.75 5 5.25 V
12
–7

°

†

4

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OD2

g

IOOutput current

,

mA

#

CC

y

SN65ALS180, SN75ALS180

DIFFERENTIAL DRIVER AND RECEIVER PAIRS

SLLS052E – AUGUST 1987 – REVISED OCTOBER 1998

DRIVERS

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS

V

IK

V

O

|V

OD1

|V

V

OD3

∆|VOD|

V

OC

∆|VOC|

I

IH

I

IL

I

OS

I

CC

†

The power-off measurement in TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.

‡

All typical values are at VCC = 5 V, TA = 25°C.

§

The minimum V

¶

∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low
level.

#

Duration of the short circuit should not exceed one second for this test.

NOTE 4: This applies for both power on and off; refer to TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does not apply for a combined

Input clamp voltage II = –18 mA –1.5 V
Output voltage IO = 0 0 6 V

| Differential output voltage IO = 0 1.5 6 V

| Differential output voltage

Differential output voltage V
Change in magnitude of

differential output voltage
Common-mode output voltage
Change in magnitude of

common-mode output voltage

p

High-level input current VI = 2.4 V 20 µA
Low-level input current VI = 0.4 V –400 µA

Short-circuit output current

Supply current No load

with 100-Ω load is either 1/2 V

OD2

driver and receiver terminal.

¶

RL = 100 Ω, See Figure 1
RL = 54 Ω, See Figure 1 1.5 2.5 5

= –7 V to 12 V, See Figure 2 1.5 5 V

test

RL = 54 Ω or 100 Ω, See Figure 1

¶

Output disabled,
See Note 4

VO = –6 V SN75ALS180 –250
VO = –4 V SN65ALS180 –250
VO = 0 All –150
VO = V

CC

VO = 8 V All

or 2 V, whichever is greater.

OD2

VO = 12 V 1
VO = –7 V –0.8

All

Driver outputs enabled,
Receiver disabled

Outputs disabled 19 26

†

MIN TYP‡MAX UNIT

1/2 V

OD1

§

or 2

25 30

±0.2 V

3

–1

±0.2 V

mA

mA

V

V

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

t

d(OD)

t

t(OD)

t

PZH

t

PZL

t

PHZ

t

PLZ

‡

All typical values are at VCC = 5 V and TA = 25°C.

Differential output delay time 3 8 13 ns
Pulse skew (t
Differential output transition time 3 8 13 ns
Output enable time to high level RL = 110 Ω, See Figure 4 23 50 ns
Output enable time to low level RL = 110 Ω, See Figure 5 19 24 ns
Output disable time from high level RL = 110 Ω, See Figure 4 8 13 ns
Output disable time from low level RL = 110 Ω, See Figure 5 8 13 ns

d(ODH)

– t

d(ODL)

)

RL = 54 Ω, CL = 50 pF, See Figure 3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1 6 ns

5

SN65ALS180, SN75ALS180

IILine input current

,

mA

CC

y

DIFFERENTIAL DRIVER AND RECEIVER PAIRS

SLLS052E – AUGUST 1987 – REVISED OCTOBER 1998

SYMBOL EQUIVALENTS

DATA-SHEET
PARAMETER

V

O

|V

| V

OD1

|V

| Vt (RL = 100 Ω) Vt (RL = 54 Ω)

OD2

|V

|

OD3

V

test

∆|VOD| ||Vt| – |Vt|| ||Vt| – |Vt||

V

OC

∆|VOC| |Vos – V

I

OS
I

O

TIA/EIA-422-B TIA/EIA-485-A

Voa, V

ob

o

|Vos| |Vos|

|

os

|Isa|, |Isb|
|Ixa|, |Ixb| Iia, I

RECEIVERS

Voa, V

ob

V

o

V

V

tst

|Vos – V

t

|

os

ib

(test termination measurement 2)

electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)

‡

†

TYP

19 30

MAX UNIT

V

mA

PARAMETER TEST CONDITIONS MIN

V

V
V

V
V
V
I

OZ

I

IH

I

IL

r

i

I

OS

I

CC

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only .

NOTE 5: This applies for both power on and power off. Refer to TIA/EIA-485-A for exact conditions.

Positive-going input threshold

IT+

voltage
Negative-going input threshold

IT–

voltage
Hysteresis voltage (V

hys

Enable-input clamp voltage II = –18 mA –1.5 V

IK

High-level output voltage VID = 200 mV, IOH = –400 µA, See Figure 6 2.7 V

OH

Low-level output voltage VID = –200 mV, IOL = 8 mA, See Figure 6 0.45 V

OL

High-impedance-state output current VO = 0.4 V to 2.4 V ±20 µA

p

High-level enable-input current VIH = 2.7 V 20 µA
Low-level enable-input current VIL = 0.4 V –100 µA
Input resistance 12 kΩ
Short-circuit output current VID = 200 mV, VO = 0 –15 –85 mA

Supply current No load

IT+

– V

IT–

VO = 2.7 V, IO = –0.4 mA 0.2 V

VO = 0.5 V, IO = 8 mA

) 60 mV

Other input = 0 V,
See Note 5

VI = 12 V 1
VI = –7 V –0.8

Receiver outputs enabled,
Driver inputs disabled

Outputs disabled 19 26

–0.2

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

See Figure 7

C

15 pF

See Figure 8

SN65ALS180, SN75ALS180

DIFFERENTIAL DRIVER AND RECEIVER PAIRS

SLLS052E – AUGUST 1987 – REVISED OCTOBER 1998

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

†

All typical values are at VCC = 5 V, TA = 25°C.

Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
Skew (|t
Output enable time to high level 7 14 ns
Output enable time to low level
Output disable time from high level
Output disable time from low level 8 17 ns

PHL

– t

PLH

|)

VID = –1.5 V to 1.5 V,

p

,

=

L

CL = 15 pF,

9 14 19 ns
9

14 19 ns

2 6 ns

7 14 ns

20 35 ns

PARAMETER MEASUREMENT INFORMATION

R

L

V

OD2

2

R

V

L

OC

2

Figure 1. Driver VOD and V

375 Ω

OD3

60 Ω

375 Ω

V

Figure 2. Driver V

CL = 50 pF

(see Note B)

Generator

(see Note A)

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

B. CL includes probe and jig capacitance.

50 Ω

3 V

TEST CIRCUIT VOLTAGE WAVEFORMS

ZO=50Ω.

RL = 54 Ω

Output

OD3

OC

Input

t

Output

V

test

d(ODH)

t

t(OD)

1.5 V 1.5 V

50%

10%

90%

50%

10%

3 V

0 V

t

d(ODL)

≈ 2.5 V
≈ –2.5 V

t

t(OD)

Figure 3. Driver Test Circuit and Voltage Waveforms

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7

SN65ALS180, SN75ALS180
DIFFERENTIAL DRIVER AND RECEIVER PAIRS

SLLS052E – AUGUST 1987 – REVISED OCTOBER 1998

PARAMETER MEASUREMENT INFORMATION

0 V or 3 V

Generator

(see Note A)

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

B. CL includes probe and jig capacitance.

50 Ω

TEST CIRCUIT VOLTAGE WAVEFORMS

ZO=50Ω.

S1

CL = 50 pF

(see Note B)

Output

RL = 110 Ω

Input

Output

1.5 V 1.5 V

t

PZH

2.3 V

t

PHZ

0.5 V

3 V

0 V

V

V

OH

off

≈ 0 V

Figure 4. Driver Test Circuit and Voltage Waveforms

5 V

0 V or 3 V

Generator

(see Note A)

50 Ω

S1

RL = 110 Ω

Output

CL = 50 pF
(see Note B)

Input

Output

t

PZL

1.5 V 1.5 V

2.3 V

t

PLZ

3 V

0 V

5 V

0.5 V
V

OL

TEST CIRCUIT

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

ZO=50Ω.

B. CL includes probe and jig capacitance.

VOLTAGE WAVEFORMS

Figure 5. Driver Test Circuit and Voltage Waveforms

V

ID

V

Figure 6. Receiver VOH and V

OL

V

OH

+I

OL

–I

OH

OL

8

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SN65ALS180, SN75ALS180

DIFFERENTIAL DRIVER AND RECEIVER PAIRS

SLLS052E – AUGUST 1987 – REVISED OCTOBER 1998

PARAMETER MEASUREMENT INFORMATION

3 V

Input

Generator

(see Note A)

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

ZO=50Ω.

B. CL includes probe and jig capacitance.

51 Ω

1.5 V
0 V

TEST CIRCUIT VOLTAGE WAVEFORMS

Output

CL = 15 pF
(see Note B)

Output

Figure 7. Receiver Test Circuit and Voltage Waveforms

1.5 V 1.5 V

t

PLH

1.3 V 1.3 V

t

PHL

0 V

V

V

OH

OL

t

PHZ

t

PZH

S1

50 Ω

1.5 V

3 V

0 V

3 V

0 V

V

1.5 V
0 V

V

≈1.3 V

TEST CIRCUIT

S1 to 1.5 V
S2 Open
S3 Closed

OH

S1 to 1.5 V
S2 Closed
S3 Closed

OH

VOLTAGE WAVEFORMS

CL = 15 pF
(see Note B)

Input

Output

Input

Output

5 kΩ

1.5 V

2 kΩ

1N916 or Equivalent

S3

t

PZL

t

PLZ

0.5 V

S2

1.5 V

3 V

1.5 V

0 V

3 V

0 V

5 V

S1 to –1.5 V
S2 Closed
S3 Open

≈4.5 V

V

OL

S1 to –1.5 V
S2 Closed
S3 Closed

≈1.3 V

V

OL

1.5 V

– 1.5 V

Generator

(see Note A)

Input

Output

Input

Output

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

1.5 V

0.5 V

ZO=50Ω.

B. CL includes probe and jig capacitance.

Figure 8. Receiver Test Circuit and Voltage Waveforms

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9

SN65ALS180, SN75ALS180
DIFFERENTIAL DRIVER AND RECEIVER PAIRS

SLLS052E – AUGUST 1987 – REVISED OCTOBER 1998

TYPICAL CHARACTERISTICS – DRIVERS

HIGH-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

5

4.5

4

3.5

3

2.5

2

1.5

– High-Level Output Voltage – V

1

OH

V

VCC = 5 V

0.5
TA = 25°C

0

0 –20 –40 –60

IOH – High-Level Output Current – mA

vs

Figure 9

–80 –100 –120

LOW-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT CURRENT

5

VCC = 5 V

4.5

TA = 25°C

4

3.5

3

2.5

2

1.5

– Low-Level Output Voltage – V

1

OL

V

0.5
0

0204060

IOL – Low-Level Output Current – mA

vs

80 100 120

Figure 10

DIFFERENTIAL OUTPUT VOLTAGE

OUTPUT CURRENT

4

3.5

3

2.5

2

1.5

– Differential Output Voltage – V

1

OD

V

0.5

VCC = 5 V
TA = 25°C

0

0102030405060

IO – Output Current – mA

Figure 11

vs

70 80 90 100

10

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SN65ALS180, SN75ALS180

DIFFERENTIAL DRIVER AND RECEIVER PAIRS

SLLS052E – AUGUST 1987 – REVISED OCTOBER 1998

TYPICAL CHARACTERISTICS – RECEIVERS

HIGH-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

5

VID = 0.2 V
TA = 25°C

4

3

2

– High-Level Output Voltage – V
V

OH

VCC = 4.75 V

1

0

0 –10 –20 –30

IOH – High-Level Output Current – mA

Figure 12

vs

VCC = 5.25 V

VCC = 5 V

–40 –50

HIGH-LEVEL OUTPUT VOLTAGE

vs

FREE-AIR TEMPERATURE

5

VCC = 5 V
VID = 200 mV
IOH = –440 µA

4

3

2

– High-Level Output Voltage – V

1

OH

V

0

–40 –20 0 20 40 60 80

TA – Free-Air Temperature – ° C

Figure 13

100 120

LOW-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT CURRENT

0.6
VCC = 5 V

TA = 25°C
VID = –200 mV

0.5

0.4

0.3

0.2

– Low-Level Output Voltage – V

OL

0.1

V

0

0510

IOL – Low-Level Output Current – mA

vs

15 20 25

Figure 14

30

LOW-LEVEL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

0.6
VCC = 5 V
VID = –200 mA
IOL = 8 mA

0.5

0.4

0.3

0.2

– Low-Level Output Voltage – VV

OL

0.1

0

–40 –20 0 20 40 60

TA – Free-Air Temperature – ° C

Figure 15

vs

80 100 120

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11

SN65ALS180, SN75ALS180
DIFFERENTIAL DRIVER AND RECEIVER PAIRS

SLLS052E – AUGUST 1987 – REVISED OCTOBER 1998

TYPICAL CHARACTERISTICS – RECEIVERS

5

VID = 0.2 V
Load = 8 kΩ to GND
TA = 25°C

4

3

2

– Output Voltage – V

O

V

1

0

VCC = 4.75 V

0 0.5 1 1.5

OUTPUT VOLTAGE

vs

ENABLE VOLTAGE

VCC = 5.25 V

2 2.5 3

VI – Enable Voltage – V

Figure 16

VCC = 5 V

6

VID = 0.2 V
Load = 1 kΩ to V
TA = 25°C

5

4

3

– Output Voltage – V

2

O

V

1

0

0 0.5 1

OUTPUT VOLTAGE

vs

ENABLE VOLTAGE

CC

VCC = 5 V

1.5 2 2.5

VI – Enable Voltage – V

Figure 17

VCC = 5.25 V

VCC = 4.75 V

3

APPLICATION INFORMATION

SN65ALS180
SN75ALS180

R

T

Up to

32 Transceivers

...

NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept

as short as possible.

R

T

Figure 18. Typical Application Circuit

SN65ALS180
SN75ALS180

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1998, Texas Instruments Incorporated