SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS020C – JUNE 1986 – REVISED MA Y 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Meets IEEE Standard 488-1978 (GPIB)
D
8-Channel Bidirectional Transceiver
D
Designed to Implement Control Bus
Interface
D
Designed for Multicontrollers
D
High-Speed Advanced Low-Power Schottky
Circuitry
D
Low-Power Dissipation...46 mW Max per
Channel
D
Fast Propagation Times . . . 20 ns Max
D
High-Impedance PNP Inputs
D
Receiver Hysteresis...650 mV Typ
D
Bus-Terminating Resistors Provided on
Driver Outputs
D
No Loading of Bus When Device Is
Powered Down (V
CC
= 0)
D
Power-Up/Power-Down Protection
(Glitch Free)
description
The SN75ALS162 eight-channel general-purpose
interface bus (GPIB) transceiver is a monolithic,
high-speed, advanced low-power Schottky process
device designed to provide the bus-management
and data-transfer signals between operating units
of a multiple-controller instrumentation system.
When combined with the SN75ALS160 octal bus
transceiver, the SN75ALS162 provides the
complete 16-wire interface for the IEEE 488 bus.
The SN75ALS162 features eight driver-receiver
pairs connected in a front-to-back configuration to
form input/output (I/O) ports at both the bus and
terminal sides. The direction of data through these
driver-receiver pairs is determined by the DC, TE,
and SC enable signals. The SC input allows the
REN and IFC transceivers to be controlled
independently.
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high
impedance to the bus when V
CC
= 0. The drivers are designed to handle loads up to 48 mA of sink current. Each
receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV minimum for
increased noise immunity . All receivers have 3-state outputs to present a high impedance to the terminal when
disabled.
The SN75ALS162 is characterized for operation from 0°C to 70°C.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DW PACKAGE
(TOP VIEW)
GPIB
I/O Ports
Terminal
I/O Ports
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
NC
GND
V
CC
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
NC
DC
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
GND
V
CC
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
DC
N PACKAGE
(TOP VIEW)
GPIB
I/O Ports
Terminal
I/O Ports
NC–No internal connection
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS020C – JUNE 1986 – REVISED MA Y 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RECEIVE/TRANSMIT FUNCTION TABLE
CONTROLS
BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS
SC DC TE ATN
†
ATN
†
SRQ REN IFC EOI DAV NDAC NRFD
(controlled by DC) (controlled by SC) (controlled by TE)
H H H
T
H H L
R
TRTRR
L L H
R
L L L
T
RTRTT
H L X R T R R T T
L H X T R T T R R
H T T
L R R
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
†
ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
CHANNEL IDENTIFICATION TABLE
NAME
IDENTITY CLASS
DC Direction Control
TE Talk Enable
Control
SC System Control
ATN Attention
SRQ Service Request
REN Remote Enable
Bus Management
IFC Interface Clear
EOI End or Identify
DAV Data Valid
NDAC No Data Accepted
Data Transfer
NRFD Not Ready for Data
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS020C – JUNE 1986 – REVISED MA Y 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
EN3
EN2/G5
2
2
2
2
NDAC
NRFD
SRQ
REN
IFC
DAV
1
1
1
16
6
6
5
7
4
3
10
13
20
19
16
18
17
NRFD
NDAC
DAV
IFC
REN
SRQ
EOI
8
15
EOI
1
1
1
1
31
11
ATN
9
EN6
4
5
ATN
14
SC
TE
≥ 1
2
2
3
3
1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
EN1/G4DC
1
2
12
3
Designates 3-state outputs
Designates passive-pullupoutputs
Pin numbers shown are for the N package.
logic diagram (positive logic)
12
DC
TE
2
EOI
EOI
15
8
9
14
ATN
ATN
SRQ
SRQ
13
10
REN
REN
20
3
4
19
IFC
IFC
7
16
DAV
DAV
NDAC
NDAC
18
5
6
17
NRFD
NRFD
SC
1
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS020C – JUNE 1986 – REVISED MA Y 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
EQUIVALENT OF ALL
CONTROL INPUTS
TYPICAL OF SRQ, NDAC, AND NRFD
GPIB I/O PORT
Circuit inside dashed lines is on the driver outputs only.
TYPICAL OF ALL I/O PORTS EXCEPT SRQ, NDAC, NRFD GPIB I/O PORTS
Receiver output R
(eq)
= 110 Ω NOM
Circuit inside dashed lines is on the driver outputs only.
R
(eq) = equivalent resistor
Driver output R
(eq)
= 30 Ω NOM
GND
Input
V
CC
NOM
9 kΩ
10 kΩ
NOM
1.7 kΩ
NOM
NOM
4 kΩ
Input/Output Port
10 kΩ
NOM
4 kΩ
NOM
R
(eq)
Input/Output Port
V
CC
GND
V
CC
GND
1.7 kΩ
NOM
4 kΩ
NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-level driver output current, I
OL
100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS020C – JUNE 1986 – REVISED MA Y 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
TA = 70°C
POWER RATING
DW 1350 mW 10.8 mW/°C 864 mW
N 1700 mW 13.6 mW/°C 1088 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
4.75 5 5.25 V
High-level input voltage, V
IH
2 V
Low level input voltage, V
IL
0.8 V
p
Bus ports with 3-state outputs – 5.2 mA
High-level output current, I
OH
Terminal ports – 800 µA
p
Bus ports 48
Low-level output current, I
OL
Terminal ports 16
mA
Operating free-air temperature, T
A
0 70 °C
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
Input clamp voltage II = –18 mA – 0.8 –1.5 V
V
hys
Hysteresis voltage
(V
IT+
– V
IT–
)
Bus 0.4 0.65 V
p
Terminal IOH = –800 µA 2.7 3.5
V
OH
‡
High-level output voltage
Bus IOH = –5.2 mA 2.5 3.3
V
p
Terminal IOL = 16 mA 0.3 0.5
VOLLow-level output voltage
Bus IOL = 48 mA 0.35 0.5
V
I
I
Input current at
maximum input voltage
Terminal VI = 5.5 V 0.2 100 µA
I
IH
High-level input current
Terminal and
VI = 2.7 V 0.1 20 µA
I
IL
Low-level input current
control inputs
VI = 0.5 V –10 –100 µA
p
I
I(bus)
= 0 2.5 3.0 3.7
V
I/O(bus)
Voltage at bus port
Driver disabled
I
I(bus)
= –12 mA –1.5
V
V
I(bus)
= –1.5 V to 0.4 V –1.3
V
I(bus)
= 0.4 V to 2.5 V 0 – 3.2
I
Current into bus port
Power on
Driver disabled
V
I(bus)
= 2.5 V to 3.7 V
+ 2.5
– 3.2
mA
I/O(bus)
V
I(bus)
= 3.7 V to 5 V 0 2.5
V
I(bus)
= 5 V to 5.5 V 0.7 2.5
Power off VCC = 0, V
I(bus)
= 0 to 2.5 V –40 µA
Short-circuit output
T erminal –15 –35 –75
I
OS
current
Bus
–25 –50 –125
mA
I
CC
Supply current No load, TE, DC, and SC low 55 75 mA
C
I/O(bus)
Bus-port capacitance VCC = 0 to 5 V, V
I/O
= 0 to 2 V, f = 1 MHz 30 pF
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
VOH applies to 3-state outputs only.
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS020C – JUNE 1986 – REVISED MA Y 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended range of operating free-air temperature, VCC = 5 V
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
MIN TYP†MAX UNIT
t
PLH
Propagation delay time,
low- to high-level output
CL = 30 pF,
10 20
t
PHL
Propagation delay time,
high- to low-level output
Terminal
Bus
L
See Figure 1
12 20
ns
t
PLH
Propagation delay time,
low- to high-level output
C
= 30 pF,
5 10
t
PHL
Propagation delay time,
high- to low-level output
Bus
Terminal
L
,
See Figure 2
7 14
ns
t
PZH
Output enable time to high level
30
t
PHZ
Output disable time from high level
Bus
(
ATN, EOI,
C
= 15 pF,
20
t
PZL
Output enable time to low level
TE, DC, or SC
(,,
REN, IFC,
L
,
See Figure 3
45
ns
t
PLZ
Output disable time from low level
and DAV)
20
t
PZH
Output enable time to high level 30
t
PHZ
Output disable time from high level
CL = 15 pF,
25
t
PZL
Output enable time to low level
TE, DC, or SC
Terminal
L
See Figure 4
30
ns
t
PLZ
Output disable time from low level 25
†
All typical values are at TA = 25°C.
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT
VOLTAGE WAVEFORMS
V
OL
V
OH
0 V
3 V
1.0 V
1.5 V
See Note B
2.2 V
1.5 V
Bus
Output
Terminal
Input
Test Point
CL =30 pF
(see Note A)
480 Ω
200 Ω
From (bus)
Output Under
Test
5 V
t
PLH
t
PHL
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, Z
O
= 50 Ω.
Figure 1. Terminal-to-Bus Load Circuit and Voltage Waveforms
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS020C – JUNE 1986 – REVISED MA Y 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT
VOLTAGE WAVEFORMS
V
OL
V
OH
0 V
3 V
1.5 V
See Note B
1.5 V
Terminal
Output
Bus
Input
Test Point
3kΩ
240 Ω
4.3 V
t
PLH
t
PHL
From (terminal)
Output Under
Test
CL =30 pF
(see Note A)
1.5 V1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, t
f
≤ 6 ns, ZO = 50 Ω.
Figure 2. Bus-to-Terminal Load Circuit and Voltage Waveforms
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS020C – JUNE 1986 – REVISED MA Y 1995
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
PZL
0.5 V
1 V
≈ 3.5 V
0 V
V
OH
0 V
3 V
90%
2 V
See Note B
Bus
Output
S1 Open
Control
Input
1.5 V1.5 V
5 V
Test Point
CL = 15 pF
(see Note A)
480 Ω
200 Ω
From (bus)
Output Under
Test
S1
LOAD CIRCUIT
VOLTAGE WAVEFORMS
V
OL
t
PZH
t
PLZ
t
PHZ
Bus
Output
S1 Closed
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
Figure 3. Bus Load Circuit and Voltage Waveforms
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS020C – JUNE 1986 – REVISED MA Y 1995
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
0.7 V
1 V
≈ 4 V
0 V
V
OH
0 V
3 V
See Note B
Terminal
Output
S1 Open
4.3 V
Test Point
3 kΩ
240 Ω
LOAD CIRCUIT
VOLTAGE WAVEFORMS
V
OL
S1
From (terminal)
Output Under
Test
CL = 15 pF
(see Note A)
t
PZH
t
PHZ
Control
Input
1.5 V1.5 V
t
PZL
t
PLZ
90%
2 V
Terminal
Output
S1 Closed
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
Figure 4. Terminal Load Circuit and Voltage Waveforms
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS020C – JUNE 1986 – REVISED MA Y 1995
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
2
1
0.5
0
0 – 5 – 10 – 15 – 20 – 25
– High-Level Output Voltage – V
3
3.5
TERMINAL
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
4
– 30 – 35 – 40
2.5
1.5
VCC = 5 V
TA = 25°C
V
OH
IOH – High-Level Output Current – mA
IOL – Low-Level Output Current – mA
TERMINAL
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
Figure 6
0.3
0.2
0.1
0
01020
– Low-Level Output Voltage – V
0.4
0.5
0.6
30 40 50 60
VCC = 5 V
TA = 25°C
V
OL
2
1.5
0.5
0
0 0.2 0.4 0.6 0.8 1 1.2
– Terminal Output Voltage
2.5
3.5
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
4
1.4 1.6 1.8 2
1
3
VCC = 5 V
No Load
TA = 25°C
V
O
VI – Bus Input Voltage – V
V
IT –
V
IT +
Figure 7
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS020C – JUNE 1986 – REVISED MA Y 1995
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
2
1
0
0 –10 – 20 – 30 – 40
– High-Level Output Voltage – V
3
BUS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
4
– 50 – 60
IOH – High-Level Output Current – mA
V
OH
VCC = 5 V
TA = 25°C
Figure 8
0.3
0.2
0.1
0
0 102030405060
– Low-Level Output Voltage – V
0.4
0.5
BUS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
70 80 90 100
IOL – Low-Level Output Current – mA
V
OL
VCC = 5 V
TA = 25°C
Figure 9
BUS OUTPUT VOLTAGE
vs
TERMINAL INPUT VOLTAGE
Figure 10
2
1
0
0.9 1 1.1 1.2 1.3 1.4
– Bus Output Voltage – V
3
4
1.5 1.6 1.7
VI – Terminal Input Voltage – V
V
O
VCC = 5 V
No Load
TA = 25°C
–1–2
–1
–2
–3
–4
–5
–6
–7
0123
– Current – mA
1
BUS
CURRENT
vs
VOLTAGE
456
0
2
I/O(bus)
I
VCC = 5 V
TA = 25°C
The Unshaded Area
Conforms to Paragraph 3.5.3
of IEEE Standard 488-1978
V
I/O(bus)
– Voltage – V
Figure 11
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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