Datasheet SN75ALS1177N, SN75ALS1177NS, SN75ALS1177NSLE, SN75ALS1177NSR, SN75ALS1178N Datasheet (Texas Instruments)
...
SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS154A – MARCH 1993 – REVISED MA Y 1995
D
Meet or Exceed Standards EIA/TIA-422-B,
RS-485, CCITT Recommendation V.11
D
Designed for Multipoint Bus Transmission
on Long Bus Lines in Noisy Environments
D
Low Supply Current Requirement
50 mA Max
D
Driver Positive- and Negative-Current
Limiting
D
Driver Common-Mode Output Voltage
Range of –7 V to 12 V
D
Thermal Shutdown Protection
D
Driver 3-State Outputs Active-High Enable
D
Receiver Common-Mode Input Voltage
Range of –12 V to 12 V
D
Receiver Input Sensitivity...±200 mV
D
Receiver Hysteresis...50 mV Typ
D
Receiver High Input Impedance
12 kΩ Min
D
Receiver 3-State Outputs Active-Low
Enable for SN75ALS1177 Only
D
Operate From Single 5-V Supply
description
The SN75ALS1177 and SN75ALS1178 dual
differential drivers and receivers are monolithic
integrated circuits designed for bidirectional data
communication on multipoint bus transmission
lines. They are designed for balanced transmission lines and meet standards EIA/TIA-422-B,
RS-485, and CCITT Recommendation V.11.
SN75ALS1177 ...N OR NS† PACKAGE
SN75ALS1178 ...N OR NS† PACKAGE
†
The NS package is only available in left-end taped and
reeled (SN75ALS1 177NSLE and SN75ALS1178SNLE).
1B
1A
1R
RE
2R
2A
2B
GND
1B
1A
1R
1DE
2R
2A
2B
GND
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
V
CC
1D
1Y
1Z
DE
2Z
2Y
9
2D
V
CC
1D
1Y
1Z
2DE
2Z
2Y
9
2D
The SN75ALS1177 combines dual 3-state differential line drivers and dual 3-state differential input line
receivers, both of which operate from a single 5-V power supply. The drivers and receivers have active-high
and active-low enables, respectively, which can be externally connected together to function as direction
control. The SN75ALS1 178 drivers each have an individual active-high enable. Fail-safe design ensures that
when the receiver inputs are open, the receiver outputs are always high.
The SN75ALS1177 and SN75ALS1178 are characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS154A – MARCH 1993 – REVISED MA Y 1995
Function Tables
SN75ALS1177, SN75ALS1178
INPUT
D DE
H H H L
L H L H
X L Z Z
DIFFERENTIAL
A – B RE Y
VID ≥ 0.2 V L H
–0.2 V < VID < 0.2 V L ?
VID ≤ – 0.2 V L L
Open L H
–0.2 V < VID < 0.2 V ?
H = high level, L = low level,
? = indeterminate, X = irrelevant,
Z = high impedance (off)
(each driver)
ENABLE
SN75ALS1177
(each receiver)
X H Z
SN75ALS1178
(each receiver)
DIFFERENTIAL
A – B Y
VID ≥ 0.2 V H
VID ≤ – 0.2 V L
Open H
OUTPUTS
Y Z
ENABLE OUTPUT
OUTPUT
2
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SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS154A – MARCH 1993 – REVISED MA Y 1995
logic symbol
DE
RE
1D
1R
2D
2R
1DE
1D
1R
2DE
2D
2R
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
†
12
4
15
3
9
5
4 14
15
3
12
9
5
SN75ALS1177
EN1
EN2
2
2
SN75ALS1178
EN
EN
1
1
1
1
14
13
10
11
13
10
11
1Y
1Z
2
1A
1
1B
2Y
2Z
6
2A
7
2B
1Y
1Z
2
1A
1
1B
2Y
2Z
6
2A
7
2B
logic diagram (positive logic)
SN75ALS1177
12
DE
4
RE
15
1D
3
1R
9
2D
5
2R
SN75ALS1178
4
1DE
15
1D
3
1R
12
2DE
9
2D
5
2R
14
13
10
11
14
13
10
11
1Y
1Z
2
1A
1
1B
2Y
2Z
6
2A
7
2B
1Y
1Z
2
1A
1
1B
2Y
2Z
6
2A
7
2B
equivalent schematics
V
CC
Input
35 kΩ NOM
Input
GND
V
CC
288 kΩ
NOM
EQUIVALENT OF RECEIVER INPUTEQUIVALENT OF DRIVER OR ENABLE INPUT
17 kΩ
VCC (A)
or
GND (B)
NOM
1.7 kΩ
NOM
1.7 kΩ
NOM
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3
SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS154A – MARCH 1993 – REVISED MA Y 1995
schematics of outputs
V
CC
Output
GND
TYPICAL OF RECEIVER OUTPUTSTYPICAL OF DRIVER OUTPUTS
V
CC
70 Ω
NOM
Output
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Output voltage range, V
Input voltage range, Receiver –14 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver differential-input voltage range (see Note 2) –14 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver low-level output current 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input voltage, are with respect to the network ground terminal.
2. Differential input voltage is measured at the noninverting terminal with respect to the inverting terminal.
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(DE, RE, and D inputs) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
PACKAGE
(Driver) –9 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
POWER RATING
N 1150 mW 9.2 mW/°C 736 mW
NS 625 mW 4.0 mW/°C 445 mW
A
DISSIPATION RATING TABLE
TA ≤ 25°C
OPERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
†
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
High-level output current, I
Low-level output current, I
mA
SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS154A – MARCH 1993 – REVISED MA Y 1995
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
Differential input voltage, V
Common-mode output voltage, V
Common-mode input voltage, V
High-level input voltage, V
Low-level input voltage, V
Operating free-air temperature, T
†
The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode
output and threshold voltage level only .
CC
ID
IC
IH
IL
p
p
OH
OL
Receiver ±12 V
Driver –7
OC
Receiver ±12 V
DE, RE, D 2 V
DE, RE, D 0.8 V
Driver –60 mA
Receiver –400 µA
Driver 60
Receiver 8
A
4.75 5 5.25 V
†
0 70 °C
12 V
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5
SN75ALS1177, SN75ALS1178
CC
,
IOSShort-circuit output current
mA
ICCSupply current (total package)
No load
mA
See Figure 3
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS154A – MARCH 1993 – REVISED MA Y 1995
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
V
OH
V
OL
|V
OD1
|V
OD2
|V
OD3
∆|VOD|
V
OC
∆|VOC|
I
O(OFF)
I
OZ
I
IH
I
IL
†
All typical values are at VCC = 5 V and TA = 25°C.
‡
The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode
output and threshold voltage levels only .
NOTES: 3. See EIA Standard RS-485 Figure 3.5, test termination measurement 2.
Input clamp voltage II = –18 mA –1.5 V
High-level output voltage VIH = 2 V, VIL = 0.8 V, IOH = –33 mA 3.3 V
Low-level output voltage VIH = 2 V, VIL = 0.8 V, IOL = 33 mA 1.1 V
| Dif ferential output voltage IO = 0 1.5 6 V
V
= 5 V,
| Dif ferential output voltage
| Dif ferential output voltage See Note 3 1.5 5 V
Change in magnitude of differential
output voltage (see Note 4)
Common-mode output voltage
Change in magnitude of common-mode
output voltage (see Note 4)
Output current with power off VCC = 0, VO = –7 V to 12 V ±100 µA
High-impedance-state output current VO = –7 V to 12 V ±100 µA
High-level input current VIH = 2.7 V 100 µA
Low-level input current VIL = 0.4 V –100 µA
p
pp
4. ∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high
level to a low level.
p
RL = 100 Ω
RL = 54 Ω 1.5 5
RL = 54 Ω or 100 Ω, See Figure 1
VO = –7 V –250
VO = V
VO = 12 V 250
VO = 0 V 150
See Figure 1
CC
Outputs enabled 35 50
Outputs disabled 20 50
1/2 V
–1
OD1
2
‡
±0.2 V
3 V
±0.2 V
250
V
switching characteristics at VCC = 5 V, TA = 25°C (unless otherwise noted)
t
Propagation delay time, high- to low-level output
PLH
t
Propagation delay time, low- to high-level output
PHL
t
Output-to-output skew
sk
t
Output enable time to high level CL = 100 pF, See Figure 4 30 35 50 ns
PZH
t
Output enable time to low level CL = 100 pF, See Figure 5 5 15 25 ns
PZL
t
Output disable time from high level CL = 15 pF, See Figure 4 7 15 30 ns
PHZ
t
Output disable time from low level CL = 15 pF, See Figure 5 7 15 30 ns
PLZ
6
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 60 Ω,
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CL1 = CL2 = 100 pF,
9 15 22 ns
9
15 22 ns
0 2 8 ns
IILine input current (see Note 5)
Other input at 0 V
mA
C
15 pF
See Figure 6
SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS154A – MARCH 1993 – REVISED MA Y 1995
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
Positive-going input threshold voltage VO = 2.7 V, IO = –0.4 mA 0.2 V
IT+
V
Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA –0.2
IT–
V
Input hysteresis voltage (V
hys
V
Enable input clamp voltage SN75ALS1 177 II = –18 mA –1.5 V
IK
V
High-level output voltage
OH
V
Low-level output voltage
OL
I
High-impedance-state output current SN75ALS1177 VO = 0.4 V to 2.4 V ±20 µA
OZ
p
I
High-level input current, RE SN75ALS1177 VIH = 2.7 V 20 µA
IH
I
Low-level input current, RE SN75ALS1177 VIL = 0.4 V –100 µA
IL
r
Input resistance 12 kΩ
i
I
Short-circuit output current VO = 0 V, See Note 6 –15 –85 mA
OS
I
Supply current (total package) No load, Outputs enabled 35 50 mA
CC
†
All typical values are at VCC = 5 V and TA = 25°C.
‡
The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode
output and threshold voltage levels only .
NOTES: 5. Refer to EIA standards RS-422-A, RS-423-A, and RS-485-A for exact conditions.
6. Not more than one output should be shorted at a time.
IT+
– V
) 50 mV
IT–
VID = 200 mV,
See Figure 2
VID = 200 mV,
See Figure 2
p
IOH = –400 µA,
IOL = 8 mA,
VI = 12 V 1
VI = –7 V –0.8
‡
2.7 V
0.45 V
V
switching characteristics at VCC = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
Output enable time to high level SN75ALS1177 CL = 100 pF, See Figure 7 10 20 30 ns
Output enable time to low level SN75ALS1177 CL = 100 pF, See Figure 7 10 20 30 ns
Output disable time from high level SN75ALS1177 CL = 15 pF, See Figure 7 5 12 16 ns
Output disable time from low level SN75ALS1177 CL = 15 pF, See Figure 7 5 12 16 ns
p
,
=
L
15 25 37 ns
15 25 37 ns
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7
SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS154A – MARCH 1993 – REVISED MA Y 1995
PARAMETER MEASUREMENT INFORMATION
R
L
2
V
OD2
R
L
V
2
OC
Figure 1. Driver Test Circuit, VOD and V
Generator
(see Note A)
NOTES: A. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
B. CL includes probe and jig capacitance.
50 Ω
3 V
DRIVER TEST CIRCUIT
60 Ω
OC
CL1 = 100 pF
(see Note B)
CL2 = 100 pF
(see Note B)
V
ID
V
OL
I
OL
Figure 2. Receiver Test Circuit, VOH and V
Driver
Input
1/2 V
Z Output
Y Output
t
PLH
O
DRIVER VOLTAGE WAVEFORMS
t
t
sk
PHL
1.5 V1.5 V
Figure 3. Driver Propagation Delay Times
V
OH
1/2 V
t
sk
I
OH
OL
3 V
0 V
O
V
O
S1
3 V or 0 V
Generator
(see Note A)
NOTES: A. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
B. CL includes probe and jig capacitance.
50 Ω
DRIVER TEST CIRCUIT
(see Note B)
Output
Input
t
C
L
RL = 500 Ω
PZH
Output
2.3 V
DRIVER VOLTAGE WAVEFORMS
1.5 V1.5 V
Figure 4. Driver Enable and Disable TImes
t
PHZ
0.5 V
3 V
0 V
V
0 V
OH
8
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SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS154A – MARCH 1993 – REVISED MA Y 1995
PARAMETER MEASUREMENT INFORMATION
V
CC
RL = 500 Ω
S1
3 V or 0 V
C
Generator
(see Note A)
NOTES: A. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
B. CL includes probe and jig capacitance.
50 Ω
DRIVER TEST CIRCUIT
(see Note B)
L
Output
Input
t
PZL
Output
2.3 V
DRIVER VOLTAGE WAVEFORMS
1.5 V1.5 V
Figure 5. Driver Enable and Disable Times
Output
Generator
(see Note A)
0 V (SN75ALS1177 only)
50 Ω
0 V
C
L
(see Note B)
1 kΩ
1 kΩ
1N916 or
Equivalent
V
CC
t
PLZ
0.5 V
3 V
0 V
0 V
V
OL
RECEIVER TEST CIRCUIT
2.5 V
Input
t
PHL
Output
DRIVER VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
B. CL includes probe and jig capacitance.
0 V0 V
–2.5 V
t
PLH
V
1.5 V1.5 V
OH
V
OL
Figure 6. Receiver Propagation Delay Times
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9
SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS154A – MARCH 1993 – REVISED MA Y 1995
PARAMETER MEASUREMENT INFORMATION
Input
Output
1.5 V
–1.5 V
Generator
(see Note A)
S1 to –1.5 V
S2 Closed
S3 Closed
S1 to 1.5 V
S2 Open
S3 Closed
S1
50 Ω
t
PZL
t
PZH
1.5 V
Output
C
L
(see Note B)
RECEIVER TEST CIRCUIT
1.5 V
1.5 V
1.5 V
S1 to –1.5 V
S2 Closed
S3 Closed
S1 to 1.5 V
S2 Open
S3 Closed
t
PLZ
t
PHZ
1 kΩ
S2
1N916 or
Equivalent
S3
0.5 V
0.5 V
1 kΩ
3 V
0 V
5 V
V
V
0 V
OL
OH
V
CC
RECEIVER VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
B. CL includes probe and jig capacitance.
Figure 7. Receiver Output Enable and Disable TImes
10
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