SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Bidirectional Transceivers
D
Meet or Exceed the Requirements of ANSI
Standards TIA/EIA-422-B and TIA/EIA-485-A
and ITU Recommendations V.11 and X.27
D
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
D
3-State Driver and Receiver Outputs
D
Individual Driver and Receiver Enables
D
Wide Positive and Negative Input/Output
Bus Voltage Ranges
D
Driver Output Capability...±60 mA Max
D
Thermal Shutdown Protection
D
Driver Positive and Negative Current
Limiting
D
Receiver Input Impedance...12 kΩ Min
D
Receiver Input Sensitivity...±200 mV
D
Receiver Input Hysteresis...50 mV Typ
D
Operate From Single 5-V Supply
description
The SN65176B and SN75176B differential bus transceivers are monolithic integrated circuits designed for
bidirectional data communication on multipoint bus transmission lines. They are designed for balanced
transmission lines and meet ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations
V.11 and X.27.
The SN65176B and SN75176B combine a 3-state differential line driver and a differential input line receiver,
both of which operate from a single 5-V power supply . The driver and receiver have active-high and active-low
enables, respectively, that can be connected together externally to function as a direction control. The driver
differential outputs and the receiver differential inputs are connected internally to form differential input/output
(I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or V
CC
= 0.
These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for
party-line applications.
The driver is designed for up to 60 mA of sink or source current. The driver features positive and negative current
limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to occur
at a junction temperature of approximately 150°C. The receiver features a minimum input impedance of 12 kΩ,
an input sensitivity of ±200 mV, and a typical input hysteresis of 50 mV.
The SN65176B and SN75176B can be used in transmission-line applications employing the SN75172 and
SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
The SN65176B is characterized for operation from – 40°C to 105°C and the SN75176B is characterized for
operation from 0°C to 70°C.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
R
RE
DE
D
V
CC
B
A
GND
D OR P PACKAGE
(TOP VIEW)
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
DRIVER
INPUT ENABLE
OUTPUTS
D DE
A B
H H H L
L H L H
X L Z Z
RECEIVER
DIFFERENTIAL INPUTS
ENABLE OUTPUT
A–B RE R
VID ≥ 0.2 V L H
–0.2 V < VID < 0.2 V L ?
VID ≤ – 0.2 V L L
X H Z
Open L ?
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
logic symbol
†
RE
DE
1
1
2
B
A
7
6
EN2
EN1
R
D
1
4
2
3
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
logic diagram (positive logic)
DE
RE
R
6
7
3
1
2
B
A
Bus
D
4
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
Output
85 Ω
NOM
TYPICAL OF RECEIVER OUTPUT
Input/Output
Port
960 Ω
NOM
16.8 kΩ
NOM
TYPICAL OF A AND B I/O PORTS
Driver input: R
(eq)
= 3 kΩ NOM
Enable inputs: R
(eq
)= 8 kΩ NOM
R
(eq)
= equivalent resistor
R
(eq)
V
CC
EQUIVALENT OF EACH INPUT
V
CC
Input
960 Ω
NOM
V
CC
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any bus terminal –10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable input voltage, V
I
5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): D package 197°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
P package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
MIN TYP MAX UNIT
Supply voltage, V
CC
4.75 5 5.25 V
p
12
Voltage at any bus terminal (separately or common mode), V
I
or
V
IC
–7
V
High-level input voltage, V
IH
D, DE, and RE 2 V
Low-level input voltage, V
IL
D, DE, and RE 0.8 V
Differential input voltage, VID (see Note 3) ±12 V
p
Driver –60 mA
High-level output current, I
OH
Receiver –400 µA
p
Driver 60
Low-level output current, I
OL
Receiver 8
mA
p
p
SN65176B –40 105
°
Operating free-air temperature, T
A
SN75176B 0 70
°C
NOTE 3: Differential-input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS
†
MIN TYP‡MAX UNIT
V
IK
Input clamp voltage II = –18 mA –1.5 V
V
O
Output voltage IO = 0 0 6 V
|V
OD1
| Differential output voltage IO = 0 1.5 3.6 6 V
|V
OD2
| Differential output voltage
RL = 100 Ω, See Figure 1
1/2 V
OD1
or 2
¶
V
OD2
g
RL = 54 Ω, See Figure 1 1.5 2.5 5 V
V
OD3
Differential output voltage See Note 4 1.5 5 V
Change in magnitude of differential output
∆|VOD|
gg
voltage
§
±0.2
V
p
+3
VOCCommon-mode output voltage
R
L
= 54 Ω or
100 Ω
,
See Figure 1
–1
V
Change in magnitude of common-mode
∆|VOC|
gg
output voltage
§
±0.2
V
p
Output disabled,
VO = 12 V 1
IOOutput current
,
See Note 5
VO = – 7 V –0.8
mA
I
IH
High-level input current VI = 2.4 V 20 µA
I
IL
Low-level input current VI = 0.4 V –400 µA
VO = –7 V –250
p
VO = 0 150
IOSShort-circuit output current
VO = V
CC
250
mA
VO = 12 V 250
pp
p
Outputs enabled 42 70
ICCSupply current (total package)
No load
Outputs disabled 26 35
mA
†
The power-off measurement in ANSI Standard TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.
‡
All typical values are at VCC = 5 V and TA = 25°C.
§
∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low
level.
¶
The minimum V
OD2
with a 100-Ω load is either 1/2 V
OD1
or 2 V, whichever is greater.
NOTES: 4. See ANSI Standard TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2.
5. This applies for both power on and off; refer to ANSI Standard TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does
not apply for a combined driver and receiver terminal.
switching characteristics, VCC = 5 V, RL = 110 kΩ, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(OD)
Differential-output delay time
15 22 ns
t
t(OD)
Differential-output transition time
R
L
= 54 Ω,
See Figure 3
20 30 ns
t
PZH
Output enable time to high level See Figure 4 85 120 ns
t
PZL
Output enable time to low level See Figure 5 40 60 ns
t
PHZ
Output disable time from high level See Figure 4 150 250 ns
t
PLZ
Output disable time from low level See Figure 5 20 30 ns
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SYMBOL EQUIVALENTS
DATA-SHEET PARAMETER
TIA/EIA-422-B TIA/EIA-485-A
V
O
V
oa, Vob
V
oa, Vob
|V
OD1
| V
o
V
o
|V
OD2
| Vt (RL = 100 Ω) Vt (RL = 54 Ω)
V
(Test Termination
|V
OD3
|
t
(
Measurement 2)
∆|VOD| ||Vt| – |Vt|| ||Vt – |Vt||
V
OC
|Vos| |Vos|
∆|VOC| |Vos – Vos| |Vos – Vos|
I
OS
|Isa|, |Isb|
I
O
|Ixa|, |Ixb| Iia, I
ib
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IT+
Positive-going input threshold voltage VO = 2.7 V, IO = –0.4 mA 0.2 V
V
IT–
Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA –0.2
‡
V
V
hys
Input hysteresis voltage (V
IT+
– V
IT–
) 50 mV
V
IK
Enable Input clamp voltage II = –18 mA –1.5 V
p
V
= 200 mV , I
= –400 µA,
VOHHigh-level output voltage
ID
,
See Figure 2
OH
µ ,
2.7
V
p
V
= –200 mV, I
= 8 mA,
VOLLow-level output voltage
ID
,
See Figure 2
OL
,
0.45
V
I
OZ
High-impedance-state output current VO = 0.4 V to 2.4 V ±20 µA
p
Other input = 0 V ,
VI = 12 V
1
IILine input current
,
See Note 6
VI = –7 V
–0.8
mA
I
IH
High-level enable input current VIH = 2.7 V 20 µA
I
IL
Low-level enable input current VIL = 0.4 V –100 µA
r
I
Input resistance VI = 12 V 12 kΩ
I
OS
Short-circuit output current –15 –85 mA
pp
p
Outputs enabled 42 55
ICCSupply current (total package)
No load
Outputs disabled 26 35
mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 6: This applies for both power on and power off. Refer to EIA Standard TIA/EIA-485-A for exact conditions.
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low- to high-level output
21 35 ns
t
PHL
Propagation delay time, high- to low-level output
V
ID
= 0 to 3 V,
See Figure 6
23 35 ns
t
PZH
Output enable time to high level
10 20 ns
t
PZL
Output enable time to low level
See Figure 7
12 20 ns
t
PHZ
Output disable time from high level
20 35 ns
t
PLZ
Output disable time from low level
See Figure 7
17 25 ns
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver VOD and VOC
2
R
L
V
OD2
V
OC
2
R
L
Figure 2. Receiver VOH and V
OL
V
ID
V
OL
V
OH
–I
OH
+I
OL
3 V
VOLTAGE WAVEFORMS
t
t(OD)
t
d(OD)
1.5 V
10%
t
t(OD)
≈ 2.5 V
≈ – 2.5 V
90%
50%
Output
t
d(OD)
0 V
3 V
1.5 V
Input
TEST CIRCUIT
Output
CL = 50 pF
(see Note A)
50 Ω
RL = 54 Ω
Generator
(see Note B)
50%
10%
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 3. Driver Test Circuit and Voltage Waveforms
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VOLTAGE WAVEFORMS
t
PHZ
1.5 V
2.3 V
0.5 V
0 V
3 V
t
PZH
Output
Input
1.5 V
S1
0 V or 3 V
Output
CL = 50 pF
(see Note A)
TEST CIRCUIT
50 Ω
V
OH
V
off
≈ 0 V
RL = 110 Ω
Generator
(see Note B)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 4. Driver Test Circuit and Voltage Waveforms
VOLTAGE WAVEFORMS
5 V
V
OL
0.5 V
t
PZL
3 V
0 V
t
PLZ
2.3 V
1.5 V
Output
Input
TEST CIRCUIT
Output
RL = 110 Ω
5 V
S1
CL = 50 pF
(see Note A)
50 Ω
3 V or 0 V
Generator
(see Note B)
1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 5. Driver Test Circuit and Voltage Waveforms
VOLTAGE WAVEFORMS
1.3 V
0 V
3 V
V
OL
V
OH
t
PHL
t
PLH
1.5 V
Output
Input
TEST CIRCUIT
CL = 15 pF
(see Note A)
Output
0 V
1.5 V
51 Ω
Generator
(see Note B)
1.5 V
1.3 V
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 6. Receiver Test Circuit and Voltage Waveforms
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
OH
0.5 V
≈ 1.3 V
t
PHZ
Output
Input
1.5 V
0 V
3 V
S1 to 1.5 V
S2 Closed
S3 Closed
t
PLZ
≈ 1.3 V
V
OL
0.5 V
Output
Input
1.5 V
0 V
3 V
≈ 4.5 V
V
OL
1.5 V
S3 Open
S2 Closed
S1 to –1.5
V
0 V
1.5 V
3 V
t
PZL
Output
Input
0 V
1.5 V
V
OH
0 V
Output
Input
t
PZH
S3 Closed
S2 Open
S1 to 1.5 V
1.5 V
3 V
TEST CIRCUIT
50 Ω
1N916 or Equivalent
S3
5 V
S2
2 kΩ
5 kΩ
S1
–1.5 V
1.5 V
VOLTAGE WAVEFORMS
S1 to –1.5 V
S2 Closed
S3 Closed
Generator
(see Note B)
CL = 15 pF
(see Note A)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 7. Receiver Test Circuit and Voltage Waveforms
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 8
VOH – High-Level Output Voltage – V
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VCC = 5 V
4.5
4
3.5
3
2.5
2
1.5
1
0.5
–100–80–60–40–20
0
–120
5
IOH – High-Level Output Current – mA
0
V
OH
TA = 25°C
Figure 9
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VCC = 5 V
TA = 25°C
IOL – Low-Level Output Current – mA
0 12020 40 60 80 100
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
– Low-Level Output Voltage – V
V
OL
VOD – Differential Output Voltage – V
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VCC = 5 V
3.5
3
2.5
2
1.5
1
0.5
908070605040302010
0
100
4
IO – Output Current – mA
0
V
OD
TA = 25°C
Figure 10
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 11
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VCC = 5.25 V
VCC = 5 V
VCC = 4.75 V
0 –10 –20 –30 –40 –50
5
0
1
2
3
4
IOH – High-Level Output Current – mA
VOH – High-Level Output Voltage – V
V
OH
4.5
3.5
2.5
1.5
0.5
–5 –15 –25
–35
–45
TA = 25°C
VID = 0.2 V
Figure 12
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
†
4
3
2
1
100806040200–20
0
120
5
TA – Free-Air Temperature – °C
–40
IOH = –440 µA
VID = 200 mV
VCC = 5 V
VOH – High-Level Output Voltage – V
V
OH
4.5
3.5
2.5
1.5
0.5
†
Only the 0°C to 70°C portion of the curve applies to the
SN75176B.
Figure 13
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TA = 25°C
VCC = 5 V
0.5
0.4
0.3
0.2
0.1
252015105
0
30
0.6
IOL – Low-Level Output Current – mA
0
VOL – Low-Level Output Voltage – V
V
OL
Figure 14
VOL – Low-Level Output Voltage – V
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VID = –200 mV
VCC = 5 V
TA – Free-Air Temperature – °C
0.6
0
0.1
0.2
0.3
0.4
0.5
100806040200–20 120–40
V
OL
IOL = 8 mA
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 15
VO – Output Voltage – V
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
VCC = 5 V
VCC = 5.25 V
TA = 25°C
VID = 0.2 V
0
VI – Enable Voltage – V
30.5 1 1.5 2 2.5
4
3
2
1
0
5
V
O
Load = 8 kΩ to GND
VCC = 4.75 V
Figure 16
VO – Output Voltage – V
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
5
4
3
2
1
2.521.510.5
0
3
6
VI – Enable Voltage – V
0
V
O
Load = 1 kΩ to V
CC
VCC = 5 V
VCC = 5.25 V
TA = 25°C
VID = –0.2 V
VCC = 4.75 V
APPLICATION INFORMATION
Up to 32
Transceivers
SN65176B
SN75176B
SN65176B
SN75176B
R
T
R
T
NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept
as short as possible.
Figure 17. Typical Application Circuit
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1999, Texas Instruments Incorporated
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