SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
D
Bidirectional Transceivers
D
Meet or Exceed the Requirements of ANSI
Standards TIA/EIA-422-B and TIA/EIA-485-A
and ITU Recommendations V.11 and X.27
D
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
D
3-State Driver and Receiver Outputs
D
Individual Driver and Receiver Enables
D
Wide Positive and Negative Input/Output
D OR P PACKAGE
(TOP VIEW)
R
RE
DE
1
2
3
D
4
8
7
6
5
V
CC
B
A
GND
Bus Voltage Ranges
D
Driver Output Capability...±60 mA Max
D
Thermal Shutdown Protection
D
Driver Positive and Negative Current
Limiting
D
Receiver Input Impedance...12 kΩ Min
D
Receiver Input Sensitivity...±200 mV
D
Receiver Input Hysteresis...50 mV Typ
D
Operate From Single 5-V Supply
description
The SN65176B and SN75176B differential bus transceivers are monolithic integrated circuits designed for
bidirectional data communication on multipoint bus transmission lines. They are designed for balanced
transmission lines and meet ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations
V.11 and X.27.
The SN65176B and SN75176B combine a 3-state differential line driver and a differential input line receiver,
both of which operate from a single 5-V power supply . The driver and receiver have active-high and active-low
enables, respectively, that can be connected together externally to function as a direction control. The driver
differential outputs and the receiver differential inputs are connected internally to form differential input/output
(I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or V
CC
= 0.
These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for
party-line applications.
The driver is designed for up to 60 mA of sink or source current. The driver features positive and negative current
limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to occur
at a junction temperature of approximately 150°C. The receiver features a minimum input impedance of 12 kΩ,
an input sensitivity of ±200 mV, and a typical input hysteresis of 50 mV.
The SN65176B and SN75176B can be used in transmission-line applications employing the SN75172 and
SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
The SN65176B is characterized for operation from – 40°C to 105°C and the SN75176B is characterized for
operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
INPUT ENABLE
D DE
H H H L
L H L H
X L Z Z
DIFFERENTIAL INPUTS
VID ≥ 0.2 V L H
–0.2 V < VID < 0.2 V L ?
VID ≤ – 0.2 V L L
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
Function Tables
DRIVER
OUTPUTS
A B
RECEIVER
ENABLE OUTPUT
A–B RE R
X H Z
Open L ?
logic symbol
DE
RE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
†
3
EN1
2
EN2
4
D
1
R
2
1
1
logic diagram (positive logic)
3
DE
4
D
2
6
A
7
B
RE
6
1
R
A
7
Bus
B
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Voltage at any bus terminal (separately or common mode), V
V
V
High-level output current, I
Low-level output current, I
mA
Operating free-air temperature, T
°C
schematics of inputs and outputs
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
EQUIVALENT OF EACH INPUT
V
CC
R
(eq)
Input
Driver input: R
Enable inputs: R
R
= equivalent resistor
(eq)
= 3 kΩ NOM
(eq)
)= 8 kΩ NOM
(eq
TYPICAL OF A AND B I/O PORTS
16.8 kΩ
NOM
Input/Output
Port
960 Ω
NOM
960 Ω
NOM
V
CC
GND
TYPICAL OF RECEIVER OUTPUT
V
CC
85 Ω
NOM
Output
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Voltage range at any bus terminal –10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable input voltage, V
Package thermal impedance, θ
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 2): D package 197°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
P package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
recommended operating conditions
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Differential input voltage, VID (see Note 3) ±12 V
p
NOTE 3: Differential-input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
CC
p
IH
IL
p
p
OH
OL
p
A
or
I
IC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MIN TYP MAX UNIT
4.75 5 5.25 V
12
–7
D, DE, and RE 2 V
D, DE, and RE 0.8 V
Driver –60 mA
Receiver –400 µA
Driver 60
Receiver 8
SN65176B –40 105
SN75176B 0 70
°
3
SN65176B, SN75176B
OD2
g
∆|VOD|
gg
±0.2
V
VOCCommon-mode output voltage
R
100 Ω
See Figure 1
V
∆|VOC|
gg
±0.2
V
IOOutput current
,
mA
IOSShort-circuit output current
mA
ICCSupply current (total package)
No load
mA
R
See Figure 3
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS
V
IK
V
O
|V
OD1
|V
OD2
V
OD3
I
IH
I
IL
†
The power-off measurement in ANSI Standard TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.
‡
All typical values are at VCC = 5 V and TA = 25°C.
§
∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low
level.
¶
The minimum V
NOTES: 4. See ANSI Standard TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2.
Input clamp voltage II = –18 mA –1.5 V
Output voltage IO = 0 0 6 V
| Differential output voltage IO = 0 1.5 3.6 6 V
| Differential output voltage
Differential output voltage See Note 4 1.5 5 V
Change in magnitude of differential output
§
voltage
p
Change in magnitude of common-mode
output voltage
p
High-level input current VI = 2.4 V 20 µA
Low-level input current VI = 0.4 V –400 µA
pp
OD2
5. This applies for both power on and off; refer to ANSI Standard TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit do es
not apply for a combined driver and receiver terminal.
§
p
p
with a 100-Ω load is either 1/2 V
RL = 100 Ω, See Figure 1
RL = 54 Ω, See Figure 1 1.5 2.5 5 V
= 54 Ω or
L
Output disabled,
See Note 5
VO = –7 V –250
VO = 0 150
VO = V
CC
VO = 12 V 250
or 2 V, whichever is greater.
OD1
,
†
VO = 12 V 1
VO = – 7 V –0.8
Outputs enabled 42 70
Outputs disabled 26 35
MIN TYP‡MAX UNIT
1/2 V
OD1
¶
or 2
+3
–1
250
V
switching characteristics, VCC = 5 V, RL = 110 kΩ, TA = 25°C (unless otherwise noted)
t
d(OD)
t
t(OD)
t
PZH
t
PZL
t
PHZ
t
PLZ
4
Differential-output delay time
Differential-output transition time
Output enable time to high level See Figure 4 85 120 ns
Output enable time to low level See Figure 5 40 60 ns
Output disable time from high level See Figure 4 150 250 ns
Output disable time from low level See Figure 5 20 30 ns
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
= 54 Ω,
L
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15 22 ns
20 30 ns
|V
|
t
(
VOHHigh-level output voltage
ID
,
OH
µ ,
2.7
V
VOLLow-level output voltage
ID
,
OL
,
0.45
V
IILine input current
,
mA
ICCSupply current (total package)
No load
mA
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
SYMBOL EQUIVALENTS
DATA-SHEET PARAMETER
V
O
|V
| V
OD1
|V
| Vt (RL = 100 Ω) Vt (RL = 54 Ω)
OD2
OD3
∆|VOD| ||Vt| – |Vt|| ||Vt – |Vt||
V
OC
∆|VOC| |Vos – Vos| |Vos – Vos|
I
OS
I
O
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IT+
V
IT–
V
hys
V
IK
I
OZ
I
IH
I
IL
r
I
I
OS
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only .
NOTE 6: This applies for both power on and power off. Refer to EIA Standard TIA/EIA-485-A for exact conditions.
Positive-going input threshold voltage VO = 2.7 V, IO = –0.4 mA 0.2 V
Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA –0.2
Input hysteresis voltage (V
Enable Input clamp voltage II = –18 mA –1.5 V
p
p
High-impedance-state output current VO = 0.4 V to 2.4 V ±20 µA
p
High-level enable input current VIH = 2.7 V 20 µA
Low-level enable input current VIL = 0.4 V –100 µA
Input resistance VI = 12 V 12 kΩ
Short-circuit output current –15 –85 mA
pp
p
IT+
– V
) 50 mV
IT–
TIA/EIA-422-B TIA/EIA-485-A
V
oa, Vob
o
|Vos| |Vos|
|Isa|, |Isb|
|Ixa|, |Ixb| Iia, I
RECEIVER SECTION
V
= 200 mV, I
See Figure 2
V
= –200 mV, I
See Figure 2
Other input = 0 V,
See Note 6
= –400 µA,
= 8 mA,
VI = 12 V
VI = –7 V
Outputs enabled 42 55
Outputs disabled 26 35
V
oa, Vob
V
o
V
(Test Termination
Measurement 2)
ib
‡
–0.8
V
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN65176B, SN75176B
V
See Figure 6
See Figure 7
See Figure 7
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
Propagation delay time, low- to high-level output
PLH
t
Propagation delay time, high- to low-level output
PHL
t
Output enable time to high level
PZH
t
Output enable time to low level
PZL
t
Output disable time from high level
PHZ
t
Output disable time from low level
PLZ
PARAMETER MEASUREMENT INFORMATION
= 0 to 3 V,
ID
21 35 ns
23 35 ns
10 20 ns
12 20 ns
20 35 ns
17 25 ns
R
L
V
OD2
2
R
L
V
OC
2
Figure 1. Driver VOD and VOC
Generator
(see Note B)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
50 Ω
3 V
TEST CIRCUIT
ZO = 50 Ω.
RL = 54 Ω
Figure 3. Driver Test Circuit and Voltage Waveforms
CL = 50 pF
(see Note A)
Output
V
ID
V
OL
Figure 2. Receiver VOH and V
Input
t
d(OD)
Output
t
t(OD)
1.5 V
50%
10%
VOLTAGE WAVEFORMS
+I
90%
OL
V
OH
1.5 V
OL
t
50%
10%
–I
d(OD)
t
t(OD)
OH
3 V
0 V
≈ 2.5 V
≈ – 2.5 V
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
S1
0 V or 3 V
CL = 50 pF
Generator
(see Note B)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
50 Ω
(see Note A)
TEST CIRCUIT
Figure 4. Driver Test Circuit and Voltage Waveforms
3 V or 0 V
CL = 50 pF
Generator
(see Note B)
50 Ω
(see Note A)
S1
Output
5 V
RL = 110 Ω
RL = 110 Ω
Output
Input
t
PZH
Output
Input
Output
1.5 V
1.5 V
2.3 V
t
PHZ
VOLTAGE WAVEFORMS
1.5 V
t
PZL
2.3 V
1.5 V
0.5 V
t
PLZ
3 V
0 V
V
V
OH
off
0.5 V
≈ 0 V
3 V
0 V
5 V
V
OL
TEST CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 5. Driver Test Circuit and Voltage Waveforms
Generator
(see Note B)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
51 Ω
1.5 V
0 V
TEST CIRCUIT
Figure 6. Receiver Test Circuit and Voltage Waveforms
Output
CL = 15 pF
(see Note A)
Input
t
Output
PLH
VOLTAGE WAVEFORMS
1.5 V
1.3 V
VOLTAGE WAVEFORMS
1.5 V
t
PHL
1.3 V
3 V
0 V
V
V
OH
OL
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN65176B, SN75176B
V
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
–1.5 V
Input
Output
Input
t
PHZ
Output
1.5 V
Generator
(see Note B)
1.5 V
0.5 V
S1
t
PZH
50 Ω
1.5 V
TEST CIRCUIT
3 V
1.5 V
S1 to 1.5 V
S2 Open
0 V
S3 Closed
V
OH
0 V
3 V
S1 to 1.5 V
S2 Closed
S3 Closed
0 V
V
OH
≈ 1.3 V
CL = 15 pF
(see Note A)
5 kΩ
Input
Output
Input
t
Output
PLZ
t
PZL
0.5 V
S2
2 kΩ
1N916 or Equivalent
S3
1.5 V
5 V
1.5 V
3 V
1.5 V
0 V
≈ 4.5 V
V
OL
3 V
S1 to –1.5 V
S2 Closed
S3 Closed
0 V
≈ 1.3 V
V
OL
S1 to –1.5
S2 Closed
S3 Open
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 7. Receiver Test Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VOLTAGE WAVEFORMS
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
TYPICAL CHARACTERISTICS
5
4.5
4
3.5
3
2.5
2
1.5
1
OH
V
VOH – High-Level Output Voltage – V
0.5
0
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0
IOH – High-Level Output Current – mA
Figure 8
VCC = 5 V
TA = 25°C
–100–80–60–40–20
–120
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
VCC = 5 V
4.5
TA = 25°C
4
3.5
3
2.5
2
1.5
1
– Low-Level Output Voltage – V
OL
V
0.5
0
0 12020 40 60 80 100
IOL – Low-Level Output Current – mA
Figure 9
4
3.5
3
2.5
2
1.5
1
OD
V
VOD – Differential Output Voltage – V
0.5
0
0
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VCC = 5 V
TA = 25°C
IO – Output Current – mA
Figure 10
908070605040302010
100
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
TYPICAL CHARACTERISTICS
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
VID = 0.2 V
4.5
TA = 25°C
4
4.5
3.5
5
4
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VCC = 5 V
VID = 200 mV
IOH = –440 µA
†
3.5
3
2.5
2
1.5
VCC = 4.75 V
1
OH
V
VOH – High-Level Output Voltage – V
0.5
0
0 –10 –20 –30 – 40 –50
–5 –15 –25
IOH – High-Level Output Current – mA
VCC = 5.25 V
VCC = 5 V
–35
Figure 11
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
0.5
VCC = 5 V
TA = 25°C
–45
3
2.5
2
1.5
1
OH
V
VOH – High-Level Output Voltage – V
0.5
0
–40
TA – Free-Air Temperature – ° C
†
Only the 0°C to 70°C portion of the curve applies to the
SN75176B.
100806040200–20
Figure 12
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
0.6
VCC = 5 V
VID = –200 mV
IOL = 8 mA
0.5
120
OL
V
VOL – Low-Level Output Voltage – V
10
0.4
0.3
0.2
0.1
0.4
0.3
0.2
OL
0.1
V
VOL – Low-Level Output Voltage – V
0
0
IOL – Low-Level Output Current – mA
252015105
30
Figure 13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0
TA – Free-Air Temperature – ° C
100806040200–20 120–40
Figure 14
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
TYPICAL CHARACTERISTICS
5
4
3
2
O
V
VO – Output Voltage – V
1
0
OUTPUT VOLTAGE
ENABLE VOLTAGE
VID = 0.2 V
Load = 8 kΩ to GND
TA = 25°C
VCC = 5 V
0
VI – Enable Voltage – V
RECEIVER
vs
Figure 15
VCC = 5.25 V
VCC = 4.75 V
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
6
VCC = 5.25 V
5
VCC = 4.75 V
4
3
2
O
V
VO – Output Voltage – V
1
0
30.5 1 1.5 2 2.5
0
VI – Enable Voltage – V
VID = –0.2 V
Load = 1 kΩ to V
TA = 25°C
VCC = 5 V
2.521.510.5
CC
3
Figure 16
APPLICATION INFORMATION
SN65176B
SN75176B
R
T
Up to 32
Transceivers
NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept
as short as possible.
R
T
Figure 17. Typical Application Circuit
SN65176B
SN75176B
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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Copyright 1999, Texas Instruments Incorporated
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