SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MA Y 1995
D
Bidirectional Transceiver
D
Meets or Exceeds the Requirements of
ANSI Standards EIA/TIA-422-B and ITU
Recommendation V.1 1
D
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
D
3-State Driver and Receiver Outputs
D
Individual Driver and Receiver Enables
D
Wide Positive and Negative Input/Output
Bus Voltage Ranges
D
Driver Output Capability...±60 mA Max
D
Thermal-Shutdown Protection
D
Driver Positive- and Negative-Current
Limiting
D
Receiver Input Impedance...12 kΩ Min
D
Receiver Input Sensitivity...±200 mV
D
Receiver Input Hysteresis...50 mV Typ
D
Operates From Single 5-V Supply
D
Low Power Requirements
description
D OR P PACKAGE
(TOP VIEW)
R
RE
DE
1
2
3
D
4
8
7
6
5
V
CC
B
A
GND
The SN75176A differential bus transceiver is a monolithic integrated circuit designed for bidirectional data
communication on multipoint bus-transmission lines. It is designed for balanced transmission lines and meets
ANSI Standard EIA/TIA-422-B and ITU Recommendation V.11.
The SN75176A combines a 3-state differential line driver and a differential input line receiver, both of which
operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables,
respectively , that can be externally connected together to function as a direction control. The driver differential
outputs and the receiver differential inputs are connected internally to form differential input /output (I/O) bus
ports that are designed to offer minimum loading to the bus whenever the driver is disabled or V
= 0. These
CC
ports feature wide positive and negative common-mode voltage ranges making the device suitable for party-line
applications.
The driver is designed to handle loads up to 60 mA of sink or source current. The driver features positive- and
negative-current limiting and thermal shutdown for protection from line fault conditions. Thermal shutdown is
designed to occur at a junction temperature of approximately 150°C. The receiver features a minimum input
impedance of 12 kΩ, an input sensitivity of ±200 mV, and a typical input hysteresis of 50 mV.
The SN75176A can be used in transmission-line applications employing the SN75172 and SN75174 quadruple
differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
The SN75176A is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MA Y 1995
INPUT ENABLE
DIFFERENTIAL INPUTS
VID ≥ 0.2 V L H
–0.2 V < VID < 0.2 V L ?
VID ≤ – 0.2 V L L
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
Function Tables
DRIVER
OUTPUTS
D DE
H H H L
L H L H
X L Z Z
RECEIVER
A – B RE R
X H Z
Open L ?
A B
ENABLE OUTPUT
logic symbol
DE
RE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
†
3
EN1
2
EN2
4
D
1
R
2
1
1
logic diagram (positive logic)
3
DE
4
D
6
A
7
B
RE
2
6
1
R
A
7
Bus
B
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE
A
schematics of inputs and outputs
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MA Y 1995
EQUIVALENT OF EACH INPUT
V
CC
R
(eq)
Input
Driver input: R
Enable inputs: R
R
= equivalent resistor
(eq)
= 3 kΩ NOM
(eq)
= 8 kΩ NOM
(eq)
TYPICAL OF A AND B I/O PORTS
16.8 kΩ
NOM
Input/Output
Port
960 Ω
NOM
960 Ω
NOM
V
CC
GND
TYPICAL OF RECEIVER OUTPUT
V
CC
85 Ω
NOM
Output
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Voltage range at any bus terminal –10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable input voltage, V
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
A
†
DISSIPATION RATING TABLE
T
≤ 25°C DERATING FACTOR T
POWER RATING ABOVE TA = 25°CAPOWER RATINGAPOWER RATING
D 725 mW 5.8 mW/°C 464 mW 261 mW
P 1100 mW 8.8 mW/°C 704 mW 396 mW
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
= 70_C T
= 105_C
3
SN75176A
High-level output current, I
Low-level output current, I
mA
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MA Y 1995
recommended operating conditions
MIN TYP MAX UNIT
Supply voltage, V
Voltage at any bus terminal (separately or common mode), VI or V
High-level input voltage, V
Low-level input voltage, V
Differential input voltage, VID (see Note 2) ±12 V
Operating free-air temperature, T
NOTE 2: Differential-input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
CC
IC
IH
IL
p
p
OH
OL
D, DE, and RE 2 V
D, DE, and RE 0.8 V
Driver –60 mA
Receiver –400 µA
Driver 60
Receiver 8
A
4.75 5 5.25 V
–7 12 V
0 70 °C
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VOHHigh-level output voltage
IH
,
IL
,
3.7
V
VOLLow-level output voltage
IH
,
IL
,
1.1
V
|V
|
Differential output voltage
V
∆|VOC|
gg
±0.2
V
IOOutput current
,
mA
ICCSupply current (total package)
No load
mA
R
See Figure 3
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MA Y 1995
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
|V
OD1
OD2
∆|V
V
OC
I
IH
I
IL
I
OS
†
All typical values are at VCC = 5 V and TA = 25°C.
‡
∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC respectively, that occur when the input is changed from a high level to a low
level.
§
In ANSI Standard EIA/TIA-422-B, VOC, which is the average of the two output voltages with respect to GND, is called output offset voltage, VOS.
NOTE 3: This applies for both power on and off; refer to ANSI Standard EIA/TIA-422-B for exact conditions.
Input clamp voltage II = –18 mA –1.5 V
V
p
p
| Differential output voltage IO = 0 2V
p
Change in magnitude of differential output voltage
OD|
Common-mode output voltage
Change in magnitude of common-mode output
‡
voltage
p
High-level input current VI = 2.4 V 20 µA
Low-level input current VI = 0.4 V –400 µA
Short-circuit output current
pp
p
§
= 2 V, V
IOH = –33 mA
V
= 2 V, V
IOH = 33 mA
RL = 100 Ω, See Figure 1 2 2.7
RL = 54 Ω, See Figure 1 1.5 2.4
‡
RL = 54 Ω or 100 Ω,
See Figure 1
Output disabled,
See Note 3
VO = –7 V –250
VO = V
CC
VO = 12 V 500
= 0.8 V,
= 0.8 V,
VO = 12 V 1
VO = – 7 V –0.8
Outputs enabled 35 50
Outputs disabled 26 40
OD2
±0.2 V
3 V
mA
250
V
switching characteristics, VCC = 5 V, TA = 25°C
t
d(OD)
t
t(OD)
t
PZH
t
PZL
t
PHZ
t
PLZ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Differential-output delay time
Differential-output transition time
Output enable time to high level RL = 110 Ω, See Figure 4 55 90 ns
Output enable time to low level RL = 110 Ω, See Figure 5 30 50 ns
Output disable time from high level RL = 110 Ω, See Figure 4 85 130 ns
Output disable time from low level RL = 110 Ω, See Figure 5 20 40 ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
= 60 Ω,
L
40 60 ns
65 95 ns
5
SN75176A
VOHHigh-level output voltage
ID
,
OH
µ ,
2.7
V
VOLLow-level output voltage
ID
,
OL
,
0.45
V
IILine input current
,
mA
ICCSupply current (total package)
No load
mA
V
See Figure 6
See Figure 7
See Figure 7
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MA Y 1995
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
V
V
V
I
OZ
I
IH
I
IL
r
i
I
OS
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only .
NOTE 3: This applies for both power on and power off. Refer to ANSI Standard EIA/TIA-422-B for exact conditions.
Positive-going input threshold voltage VO = 2.7 V, IO = –0.4 mA 0.2 V
IT+
Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA –0.2
IT–
Input hysteresis voltage (V
hys
Enable clamp voltage II = –18 mA –1.5 V
IK
p
p
High-impedance-state output current VO = 0.4 V to 2.4 V ±20 µA
p
High-level enable input current VIH = 2.7 V 20 µA
Low-level enable input current VIL = 0.4 V –100 µA
Input resistance 12 kΩ
Short-circuit output current –15 –85 mA
pp
p
IT+
– V
) 50 mV
IT–
V
= 200 mV, I
See Figure 2
V
= –200 mV, I
See Figure 2
Other input = 0 V,
See Note 3
= –400 µA,
= 8 mA,
VI = 12 V 1
VI = –7 V –0.8
Outputs enabled 35 50
Outputs disabled 26 40
‡
V
switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
Propagation delay time, low-to-high-level output
PLH
t
Propagation delay time, high-to-low-level output
PHL
t
Output enable time to high level
PZH
t
Output enable time to low level
PZL
t
Output disable time from high level
PHZ
t
Output disable time from low level
PLZ
= –1.5 V to 1.5 V,
ID
21 35 ns
23 35 ns
10 30 ns
12 30 ns
20 35 ns
17 25 ns
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MA Y 1995
PARAMETER MEASUREMENT INFORMATION
R
V
OD2
L
2
R
L
V
OC
2
V
ID
0 V
V
OL
V
OH
+I
OL
–I
OH
Figure 1. Driver VOD and VOC
CL = 50 pF
Generator
(see Note A)
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
B. CL includes probe and jig capacitance.
50 Ω
3 V
TEST CIRCUIT
ZO = 50 Ω.
RL = 60 Ω
(see Note B)
C
L
Output
Figure 2. Receiver VOH and V
Input
t
d(OD)
Output
1.5 V
50%
10%
t
t(OD)
VOLTAGE WAVEFORMS
1.5 V
90%
OL
t
50%
10%
d(OD)
t
t(OD)
3 V
0 V
≈ 2.5 V
≈ – 2.5 V
Figure 3. Driver Test Circuit and Voltage Waveforms
0 or 3 V
Generator
(see Note A)
50 Ω
S1
CL = 50 pF
(see Note B)
Output
RL = 110 Ω
Input
t
Output
PZH
1.5 V
1.5 V
2.3 V
t
PHZ
3 V
0 V
0.5 V
V
OH
V
≈ 0 V
off
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
VOLTAGE WAVEFORMS
Figure 4. Driver Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MA Y 1995
5 V
S1
3 V or 0
CL = 50 pF
Generator
(see Note A)
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
B. CL includes probe and jig capacitance.
50 Ω
TEST CIRCUIT
ZO = 50 Ω.
(see Note B)
RL = 110 Ω
Output
Input
Output
t
PZL
1.5 V
VOLTAGE WAVEFORMS
1.5 V
2.3 V
t
PLZ
3 V
0 V
5 V
0.5 V
V
OL
Figure 5. Driver Test Circuit and Voltage Waveforms
3 V
Generator
(see Note A)
51 Ω
1.5 V
0 V
TEST CIRCUIT
Output
CL = 15 pF
(see Note B)
Input
t
Output
PLH
1.5 V
1.3 V
VOLTAGE WAVEFORMS
1.5 V
t
PHL
1.3 V
0 V
V
V
OH
OL
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 6. Receiver Test Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MA Y 1995
–1.5 V
Input
Output
Input
t
PHZ
Output
1.5 V
Generator
(see Note A)
0.5 V
1.5 V
S1
t
PZH
50 Ω
1.5 V
3 V
1.5 V
0 V
3 V
0 V
TEST CIRCUIT
S1 to 1.5 V
S2 Open
S3 Closed
V
OH
0 V
S1 to 1.5 V
S2 Closed
S3 Closed
V
OH
≈ 1.3 V
CL = 15 pF
(see Note B)
5 kΩ
Input
Output
Input
t
Output
PLZ
t
PZL
0.5 V
S2
2 kΩ
1N916 or Equivalent
S3
1.5 V
5 V
1.5 V
3 V
0 V
3 V
1.5 V
S1 to –1.5 V
S2 Closed
0 V
S3 Open
≈ 4.5 V
V
OL
S1 to –1.5 V
S2 Closed
S3 Closed
≈ 1.3 V
V
OL
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 7. Receiver Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MA Y 1995
TYPICAL CHARACTERISTICS
5
4.5
4
3.5
3
2.5
2
1.5
1
OH
V
VOH – High-Level Output Voltage – V
0.5
0
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0
IOH – High-Level Output Current – mA
Figure 8
VCC = 5 V
TA = 25°C
–100–80–60–40–20
–120
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
VCC = 5 V
4.5
TA = 25°C
4
3.5
3
2.5
2
1.5
1
– Low-Level Output Voltage – V
OL
V
0.5
0
0 12020 40 60 80 100
IOL – Low-Level Output Current – mA
Figure 9
4
3.5
3
2.5
2
1.5
1
OD
V
VOD – Differential Output Voltage – V
0.5
0
0
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VCC = 5 V
TA = 25°C
IO – Output Current – mA
Figure 10
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
VCC = 5 V
TA = 25°C
0.5
0.4
0.3
0.2
OL
0.1
V
VOL – Low-Level Output Voltage – V
908070605040302010
100
0
0510
IOL – Low Level Output Current – mA
15 20 25
30
Figure 11
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MA Y 1995
TYPICAL CHARACTERISTICS
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
0.5
VCC = 5 V
VID = –0.2 V
IOL = 8 mA
0.4
0.3
0.2
0.1
OL
V
VOL – Low-Levcel Output Voltage – V
0
0203050
10 40 60
TA – Free-Air Temperature – ° C
Figure 12
70 80
5
VID = 0.2 V
Load = 8 kΩ to GND
TA = 25°C
4
3
2
O
VO – Output Voltage – V
V
1
0
0 0.5 1 1.5
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
VCC = 5 V
VI – Enable Voltage – V
VCC = 4.75 V
Figure 13
VCC = 5.25 V
2 2.5 3
6
5
4
3
2
O
VO – Output Voltage – V
V
1
0
0 0.5 1
OUTPUT VOLTAGE
ENABLE VOLTAGE
VCC = 5.25 V
VCC = 4.75 V
VI – Enable Voltage – V
RECEIVER
vs
VID = 0.2 V
Load = 1 kΩ to V
TA = 25°C
VCC = 5 V
1.5 2 2.5
Figure 14
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MA Y 1995
APPLICATION INFORMATION
SN65176A
R
T
Up to 32
Transceivers
NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept
as short as possible.
R
T
SN65176A
Figure 15. Typical Application Circuit
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1998, Texas Instruments Incorporated
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