Datasheet SN75161BN, SN75162BDW, SN75162BDWR, SN75162BN, SN75161BDW Datasheet (Texas Instruments)
...
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MA Y 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Meets IEEE Standard 488-1978 (GPIB)
D
8-Channel Bidirectional Transceivers
D
Power-Up/Power-Down Protection
(Glitch Free)
D
Designed to Implement Control Bus
Interface
D
SN75161B Designed for Single Controller
D
SN75162B Designed for Multiple
Controllers
D
High-Speed, Low-Power Schottky Circuitry
D
Low Power Dissipation...72 mW Max Per
Channel
D
Fast Propagation Times . . . 22 ns Max
D
High-Impedance pnp Inputs
D
Receiver Hysteresis...650 mV Typ
D
Bus-Terminating Resistors Provided on
Driver Outputs
D
No Loading of Bus When Device Is
Powered Down (V
CC
= 0)
description
The SN75161B and SN75162B eight-channel,
general-purpose interface bus transceivers are
monolithic, high-speed, low-power Schottky
devices designed to meet the requirements of
IEEE Standard 488-1978. Each transceiver is
designed to provide the bus-management and
data-transfer signals between operating units of
a single- or multiple-controller instrumentation
system. When combined with the SN75160B octal
bus transceiver, the SN75161B or SN75162B
provides the complete 16-wire interface for the
IEEE-488 bus.
The SN75161B and SN75162B feature eight
driver-receiver pairs connected in a front-to-back
configuration to form input/output (I/O) ports at
both the bus and terminal sides. A powerup/-down disable circuit is included on all bus and
receiver outputs. This provides glitch-free operation during V
CC
power up and power down.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
NC
GND
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
V
CC
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
NC
DC
(TOP VIEW)
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
GND
V
CC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
DC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GPIB
I/O Ports
Terminal
I/O Ports
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
GND
V
CC
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
DC
(TOP VIEW)
NC–No internal connection
SN75161B . . . DW OR N PACKAGE
SN75162B . . . DW PACKAGE
SN75162B ...N PACKAGE
GPIB
I/O Ports
Terminal
I/O Ports
GPIB
I/O Ports
Terminal
I/O Ports
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MA Y 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The direction of data through these driver-receiver pairs is determined by the DC, TE, and SC (on SN75162B)
enable signals. The SC input on the SN75162B allows the REN and IFC transceivers to be controlled
independently.
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high
impedance to the bus when supply voltage V
CC
is 0. The drivers are designed to handle loads up to 48 mA of
sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV
for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the terminal
when disabled.
The SN75161B and SN75162B are characterized for operation from 0°C to 70°C.
Function Tables
SN75161B RECEIVE/TRANSMIT
CONTROLS
BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS
DC TE
ATN
†
ATN
†
SRQ REN IFC EOI DAV NDAC NRFD
(Controlled by DC) (Controlled by TE)
H H H
T
H H L
RTR
RRTRR
L L H
R
L L L
TRT
TTRTT
H L X R T R R R R T T
L H X T R T T T T R R
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
†
ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
SN75162B RECEIVE/TRANSMIT
CONTROLS
BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS
SC DC TE
ATN
†
ATN
†
SRQ REN IFC EOI DAV NDAC NRFD
(Controlled by DC) (Controlled by SC) (Controlled by TE)
H H H
T
H H L
R
TRTRR
L L H
R
L L L
T
RTRTT
H L X R T R R T T
L H X T R T T R R
H T T
L R R
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
†
ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MA Y 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CHANNEL-IDENTIFICATION TABLE
NAME
IDENTITY CLASS
DC Direction Control
TE Talk Enable Control
SC System Control (SN75162B only)
ATN Attention
SRQ Service Request
REN Remote Enable Bus
IFC Interface Clear Management
EOI End of Identity
DAV Data Valid
NDAC Not Data Accepted Data
NRFD Not Ready for Data Transfer
SN75161B logic symbol
†
EN3
1
ATN
8
1
ATN
13
1
1
EOI
7
3
EOI
14
1
3
SRQ
1
SRQ
12
1
1
REN
2
1
REN
19
1
1
IFC
3
1
IFC
18
1
1
DAV
6
2
DAV
15
1
2
NDAC
4
2
NDAC
17
1
2
2
1
16
NRFD
2
EN1/G4
EN2/G5
5
4
5
NRFD
TE
1
DC
11
This symbol is in accordance with IEEE Std 91-1984 and
IEC Publication 617-12.
Designates 3-state outputs
Designates passive-pullup outputs
{
9
SN75161B logic diagram (positive logic)
NRFD
5
NRFD
16
NDAC
4
NDAC
17
DAV
6
DAV
15
IFC
3
IFC
18
REN
2
REN
19
SRQ
9
SRQ
12
EOI
7
EOI
14
11
DC
1
TE
13
ATN
8
ATN
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MA Y 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75162B logic symbol
†
EN3
≥ 1
ATN
1
ATN
14
1
1
EOI
6
EOI
1
6
SRQ
1
SRQ
1
1
REN
REN
1
3
IFC
IFC
1
DAV
2
DAV
1
2
NDAC
2
NDAC
1
2
2
1
NRFD
2
EN1/G4
EN2/G5
5
4
NRFD
TE
DC
This symbol is in accordance with IEEE Std 91-1984 and
IEC Publication 617-12.
Designates 3-state outputs
Designates passive-pullup outputs
{
EN3
12
2
1
15
SC
13
20
19
16
18
17
9
8
10
3
4
7
5
6
3
3
3
Pin numbers shown are for the N package.
SN75162B logic diagram (positive logic)
NRFDNRFD
NDACNDAC
DAVDAV
IFCIFC
RENREN
SRQSRQ
EOIEOI
DC
TE
ATN ATN
12
2
1
14
15
13
20
19
16
18
17
9
8
10
3
4
7
5
6
SC
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MA Y 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
NOM
4 kΩ
R
(eq)
1.7 kΩ
NOM
10 kΩ
NOM
V
CC
GND
Input/Output Port
Input/Output Port
GND
V
CC
NOM
10 kΩ
NOM
4 kΩ
NOM
1.7 kΩ
NOM
9 kΩ
GND
Input
V
CC
NOM
4 kΩ
EQUIVALENT OF ALL CONTROL INPUTS TYPICAL OF SRQ, NDAC, AND NRFD GPIB I/O PORT
Circuit inside dashed lines is on the driver outputs only.
TYPICAL OF ALL I/O PORTS EXCEPT SRQ, NDAC,
AND NRFD GPIB I/O PORTS
Driver output R
(eq)
= 30 Ω NOM
Receiver output R
(eq)
= 110 Ω NOM
Circuit inside dashed lines is on the driver outputs only.
R
(eq)
= equivalent resistor
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-level driver output current, I
OL
100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16) inch from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MA Y 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
DW (20 pin) 1125 mW 9.0 mW/°C 720 mW
DW (24 pin) 1350 mW 10.8 mW/°C 864 mW
N (20 pin) 1150 mW 9.2 mW/°C 736 mW
N (22 pin) 1700 mW 13.6 mW/°C 1088 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
4.75 5 5.25 V
High-level input voltage, V
IH
2 V
Low-level input voltage, V
IL
0.8 V
p
Bus ports with 3-state outputs –5.2 mA
High-level output current, I
OH
Terminal ports –800 µA
p
Bus ports 48
Low-level output current, I
OL
Terminal ports 16
mA
Operating free-air temperature, T
A
0 70 °C
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MA Y 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN
TYP
†
MAX UNIT
V
IK
Input clamp voltage II = –18 mA –0.8 –1.5 V
V
hys
Hysteresis voltage
(V
IT+
– V
IT–
)
Bus See Figure 7 0.4 0.65 V
p
Terminal IOH = –800 µA 2.7 3.5
V
OH
‡
High-level output voltage
Bus IOH = –5.2 mA 2.5 3.3
V
p
Terminal IOL = 16 mA 0.3 0.5
VOLLow-level output voltage
Bus IOL = 48 mA 0.35 0.5
V
Input current at maximum
I
I
input voltage
Terminal
V
I
= 5.5
V
0.2
100µA
I
IH
High-level input current
Terminal and
VI = 2.7 V 0.1 20 µA
I
IL
Low-level input current
control inputs
VI = 0.5 V –10 –100 µA
p
I
I(bus)
= 0 2.5 3.0 3.7
V
I/O(bus)
Voltage at bus port
Driver disabled
I
I(bus)
= –12 mA –1.5
V
V
I(bus)
= –1.5 V to 0.4 V –1.3
V
I(bus)
= 0.4 V to 2.5 V 0 –3.2
2.5
I
I/O(bus)
Current into bus port
Power on
Driver disabled
V
I(bus)
= 2.5 V to 3.7
V
–3.2
mA
()
V
I(bus)
= 3.7 V to 5 V 0 2.5
V
I(bus)
= 5 V to 5.5 V 0.7 2.5
Power off VCC = 0, V
I(bus)
= 0 V to 2.5 V –40 µA
p
Terminal –15 –35 –75
IOSShort-circuit output current
Bus –25 –50 –125
mA
I
CC
Supply current No load, TE, DE, and SC low 110 mA
p
p
VCC = 5 V to 0,
p
C
I/O(bus)
Bus-port capacitance
CC
V
I/O
= 0 to 2 V, f = 1 MHz
16
pF
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
VOH applies for 3-state outputs only.
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MA Y 1995
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, V
CC
= 5 V, CL = 15 pF, TA = 25°C (unless otherwise noted)
PARAMETER
FROM
(INPUT)TO(OUTPUT)
TEST
CONDITIONS
MIN TYP MAX UNIT
t
PLH
Propagation delay time,
low- to high-level output
CL = 30 pF,
14 20
t
PHL
Propagation delay time,
high- to low-level output
Terminal
Bus
L
See Figure 1
14 20
ns
t
PLH
Propagation delay time,
low- to high-level output
Terminal
Bus
(SRQ,NDAC,
NRFD)
CL = 30 pF,
See Figure 1
29 35 ns
t
PLH
Propagation delay time,
low- to high-level output
CL = 30 pF,
10 20
t
PHL
Propagation delay time,
high- to low-level output
Bus
Terminal
L
See Figure 2
15 22
ns
t
PZH
Output enable time to high level
60
t
PHZ
Output disable time from high level
TE,DC,
Bus (ATN
,
EOI, REN,
45
t
PZL
Output enable time to low level
or
SC
,,
IFC, and
See Figure 3
60
ns
t
PLZ
Output disable time from low level
SC
DAV)
55
t
PZH
Output enable time to high level 55
t
PHZ
Output disable time from high level
TE,DC,
50
t
PZL
Output enable time to low level
or
SC
Terminal
See Figure 4
45
ns
t
PLZ
Output disable time from low level
SC
55
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MA Y 1995
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
LOAD CIRCUIT
480 Ω
200 Ω
(see Note A)
CL = 30 pF
Test Point
5 V
Output
Bus
Input
Terminal
See Note B
V
OH
V
OH
0 V
3 V
t
PHL
2.2 V
1.0 V
1.5 V
t
PLH
1.5 V
From (Bus)
Output Under
Test
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
Figure 1. Terminal-to-Bus Load Circuit and Voltage Waveforms
See Note B
1.5 V
t
PLH
1.5 V
1.5 V
1.5 V
t
PHL
3 V
0 V
V
OH
V
OL
Bus
Input
Output
From (Terminal)
Output Under
Test
4.3 V
Test Point
CL = 30 pF
(see Note A)
240 Ω
3 kΩ
LOAD CIRCUIT
VOLTAGE WAVEFORMS
Terminal
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
Figure 2. Bus-to-Terminal Load Circuit and Voltage Waveforms
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MA Y 1995
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
S1 Open
t
PHZ
1.5 V
3 V
0 V
S1 Closed
1 V
3.5 V
V
OL
Input
Control
See Note B
1.5 V
t
PZH
S1
VOLTAGE WAVEFORMS
2 V
t
PZL
90%
0.5 V
t
PLZ
V
OH
0 V
Bus
Output
Bus
Output
5 V
Test Point
CL = 15 pF
(see Note A)
200 Ω
480 Ω
LOAD CIRCUIT
From (Bus)
Output Under
Test
Figure 3. Bus Enable and Disable Times Load Circuit and Voltage Waveforms
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MA Y 1995
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
90%
Output
Terminal
S1 Open
S1 Closed
Terminal
t
PHZ
VOLTAGE WAVEFORMS
Output
0 V
V
OH
t
PLZ
0.7 V
t
PZL
1.5 V
t
PZH
1.5 V
See Note B
Control
Input
V
OL
4 V
1 V
0 V
3 V
1.5 V
LOAD CIRCUIT
3 kΩ
240 Ω
Test Point
4.3 V
S1
CL = 15 pF
(see Note A)
From (Terminal)
Output Under
Test
NOTES: A. CL includes probe and jig capacitance.
B. The Input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 4. Terminal Enable and Disable Times Load Circuit and Voltage Waveforms
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MA Y 1995
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
VOH – High-Level Output Voltage – V
TERMINAL I/O PORTS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
3
2.5
2
1.5
1
0.5
–35–30–25–20–15–10–5
0
–40
4
0
TA = 25°C
VCC = 5 V
IOH – High-Level Output Current – mA
V
OH
Figure 5
IOL – Low-Level Output Current – mA
VOL – Low-Level Output Voltage – V
TERMINAL I/O PORTS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TA = 25°C
VCC = 5 V
0.5
0.4
0.3
0.2
0.1
5040302010
0
60
0.6
0
V
OL
Figure 6
2
VO – Output Voltage – V
TERMINAL I/O PORTS
OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
V
IT–
TA = 25°C
No Load
VCC = 5 V
3.5
3
2.5
2
1.5
1
0.5
1.81.61.41.210.80.60.40.2
0
4
VI – Bus Input Voltage – V
0
V
O
V
IT+
Figure 7
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MA Y 1995
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
IOH – High-Level Output Current – mA
– High-Level Output Voltage – V
GPIB I/O PORTS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
TA = 25°C
VCC = 5 V
3
2
1
–50–30–40–20–10
0
–60
0
0
V
OH
Figure 8
IOL – Low-Level Output Current – mA
– Low-Level Output Voltage – V
GPIB I/O PORTS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TA = 25°C
VCC = 5 V
0.5
0.4
0.3
0.2
0.1
908070605040302010
0
100
0.6
0
V
OL
Figure 9
Figure 10
VI – Input Voltage – V
VO – Output Voltage – V
GPIB I/O PORTS
OUTPUT VOLTAGE
vs
THERMAL INPUT VOLTAGE
TA = 25°C
No Load
VCC = 5 V
3
2
1
1.61.51.41.31.21.11
0
4
0.9 1.7
V
O
– Current – mA
GPIB I/O PORTS
CURRENT
vs
VOLTAGE
2
1
0
–1
–2
–3
–6
543210–1
–7
6
V
I/O
– Voltage – V
–2
TA = 25°C
VCC = 5 V
The Unshaded
Area Conforms to
Paragraph 3.5.3 of
IEEE Standard 488-1978
I
I/O
–5
–4
Figure 11
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