SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUARY 1990 – REVISED MAY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Meet or Exceed the Requirements of ANSI
Standards TIA/EIA-422-B and TIA/EIA-485-A
and ITU Recommendations V.10 and V.11
D
Designed for Multipoint Bus Transmission
on Long Bus Lines in Noise Environments
D
Driver Positive- and Negative-Current
Limiting
D
Thermal Shutdown Protection
D
Driver 3-State Outputs
D
Receiver Common-Mode Input Voltage
Range of –12 V to 12 V
D
Receiver Input Sensitivity...±200 mV
D
Receiver Hysteresis...50 mV Typ
D
Receiver Input Impedance...12kΩ Min
D
Receiver 3-State Outputs (SN751177 Only)
D
Operate From Single 5-V Supply
description
The SN751177 and SN751178 dual differential
drivers and receivers are monolithic integrated
circuits that are designed for balanced multipoint
bus transmission at rates up to 10 Mbit/s. They are
designed to improve the performance of
full-duplex data communications over long bus
lines and meet ANSI Standards TIA/EIA-422-B
and TIA/EIA-485-A and ITU Recommendations
V.10 and V.11.
The SN751177 and SN751178 driver outputs provide limiting for both positive and negative currents and
thermal-shutdown protection from line-fault conditions on the transmission bus line.
The receiver features high input impedance of at least 12 kΩ, an input sensitivity of ±200 mV over a
common-mode input voltage range of –12 V to 12 V, and typical input hysteresis of 50 mV. Fail-safe design
ensures that if the receiver inputs are open, the receiver outputs always will be high.
The SN751177 and SN751178 are characterized for operation from –20°C to 85°C.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1R
RE
2R
2A
2B
GND
V
CC
1D
1Y
1Z
DE
2Z
2Y
2D
SN751177 ...N OR NS† PACKAGE
(TOP VIEW)
†
The NS package is only available taped and reeled.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1R
1DE
2R
2A
2B
GND
V
CC
1D
1Y
1Z
2DE
2Z
2Y
2D
SN751178 ...N OR NS† PACKAGE
(TOP VIEW)
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUARY 1990 – REVISED MAY 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
SN751177, SN751178
(each driver)
INPUT
ENABLE
OUTPUTS
D DE
Y Z
H H H L
L H L H
X L Z Z
H = high level, L = low level, X = irrelevant,
Z = high impedance (off)
SN751177
(each receiver)
DIFFERENTIAL INPUTS
A – B
ENABLEREOUTPUT
R
VID ≥ 0.2 V L H
–0.2 V < VID < 0.2 V L ?
VID ≤ –0.2 V L L
X H Z
Open L H
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
SN751178
(each receiver)
DIFFERENTIAL INPUTS
A – B
OUTPUT
R
VID ≥ 0.2 V H
–0.2 V < VID < 0.2 V ?
VID ≤ –0.2 V L
H = high level, L = low level,
? = indeterminate
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUARY 1990 – REVISED MAY 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbols
†
SN751177
SN751178
1
1
1
1
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
EN1
12
DE
EN2
4
15
1D
1R
3
9
2D
2R
5
2
2
1Y
14
1Z
13
1A
2
1B
1
2Y
10
2Z
11
2A
6
2B
7
EN
4
1DE
15
1D
1R
3
EN
12
2DE
9
2D
2R
5
1Y
14
1Z
13
1A
2
1B
1
2Y
10
2Z
11
2A
6
2B
7
RE
logic diagrams (positive logic)
RE
DE
SN751177
SN751178
12
4
15
14
13
2
1
3
9
10
11
6
7
5
1D
1R
2D
2R
2B
2A
2Z
2Y
1B
1A
1Z
1Y
15
14
13
1D
1Z
1Y
4
1DE
2
1
3
1R
1B
1A
9
10
11
2D
2Z
2Y
12
2DE
6
7
5
2R
2B
2A
schematics of inputs
EQUIVALENT OF RECEIVER INPUTEQUIVALENT OF DRIVER OR ENABLE INPUT
Input
V
CC
Driver Input: R
(eq)
= 6 kΩ NOM
Enable Input: R
(eq)
= 4 kΩ NOM
R
(eq)
= Equivalent Resistor
Input
V
CC
R
(eq)
All resistor values are nominal.
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUARY 1990 – REVISED MAY 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of outputs
TYPICAL OF ALL RECEIVER OUTPUTSTYPICAL OF ALL DRIVER OUTPUTS
Output
85 Ω
NOM
V
CC
GND
Output
V
CC
All resistor values are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
(DE, RE, and D inputs) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver input voltage range, V
I
(A or B inputs) –25 V to 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver differential input voltage range, V
ID
(see Note 2) –25 V to 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver output voltage range, V
O
–10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver low-level output current, I
OL
50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3): N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 111°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input voltage, are with respect to the network ground terminal.
2. Differential input voltage is measured at the noninverting terminal with respect to the inverting terminal.
3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUARY 1990 – REVISED MAY 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
4.75 5 5.25 V
High-level input voltage, V
IH
2 V
Low-level input voltage, V
IL
DE, RE
, and D inputs
0.8 V
Common-mode output voltage, V
OC
–7
†
12 V
High-level output current, I
OH
Driver
–60 mA
Low-level output current, I
OL
60 mA
Common-mode input voltage, V
IC
±12 V
Differential input voltage, V
ID
±12 V
High-level output current, I
OH
Receiver
–400 µA
Low-level output current, I
OL
16 mA
Operating free-air temperature, T
A
–20 85 °C
†
The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode
output and threshold voltage levels only .
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUARY 1990 – REVISED MAY 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DRIVER SECTIONS
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN
TYP
†
MAX UNIT
V
IK
Input clamp voltage II = –18 mA –1.5 V
V
OH
High-level output voltage VIH = 2 V, VIL = 0.8 V, IOH = –33 mA 3.7 V
V
OL
Low-level output voltage VIH = 2 V, VIL = 0.8 V, IOH = 33 mA 1.1 V
|V
OD1
| Differential output voltage IO = 0 1.5 6 V
2 or
|V
OD2
| Differential output voltage
R
L
=
100 Ω
,
See Figure 1
1/2 V
OD1
‡
V
OD2
g
RL = 54 Ω, See Figure 1 1.5 5
V
OD3
Differential output voltage See Note 4 1.5 5 V
∆|VOD|
Change in magnitude of
differential output voltage (see Note 5)
±0.2 V
V
OC
Common-mode output voltage
RL = 54 Ω or 100 Ω, See Figure 1
–1
§
3 V
∆|VOC|
Change in magnitude of
common-mode output voltage (see Note 5)
±0.2 V
I
O
Output current with power off VCC = 0, VO = –7 V to 12 V ±100 µA
I
OZ
High-impedance-state output current VO = –7 V to 12 V ±100 µA
I
IH
High-level input current VIH = 2.7 V 20 µA
I
IL
Low-level input current VIL = 0.4 V –100 µA
VO = –7 V –250
I
OS
Short-circuit output current (see Note 6)
VO = V
CC
250
mA
VO = 12 V 250
pp
Outputs enabled 80 110
ICCSupply current
No load
Outputs disabled 50 80
mA
†
All typical values are at VCC = 5 V and TA = 25°C.
‡
The minimum V
OD2
with a 100-Ω load is either 1/2 V
OD1
or 2 V, whichever is greater.
§
The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode
output and threshold voltage levels only .
NOTES: 4. See TIA/EIA-485-A Figure 3.5, Test Termination Measurement 2
5. ∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high
level to a low level.
6. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
switching characteristics at VCC = 5 V, CL = 50 pF, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(OD)
Differential output delay time
20 25 ns
t
t(OD)
Differential output transition time
R
L
= 54 Ω,
See Figure 3
27 35 ns
t
PLH
Propagation delay time, low- to high-level output
20 25 ns
t
PHL
Propagation delay time, high- to low-level output
R
L
= 27 Ω,
See Figure 4
20 25 ns
t
PZH
Output enable time to high level RL = 110 Ω, See Figure 5 80 120 ns
t
PZL
Output enable time to low level RL = 110 Ω, See Figure 6 40 60 ns
t
PHZ
Output disable time from high level RL = 110 Ω, See Figure 5 90 120 ns
t
PLZ
Output disable time from low level RL = 110 Ω, See Figure 6 30 45 ns
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUARY 1990 – REVISED MAY 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SYMBOL EQUIVALENTS
DATA-SHEET
PARAMETER
TIA/EIA-422-B TIA/EIA-485-A
|V
OD1
| V
O
V
O
|V
OD2
| Vt (RL = 100 Ω) Vt (RL = 54 Ω)
|V
OD3
|
Vt (Test Termination
Measurement 2)
∆|VOD| | |Vt| – |Vt| | | |Vt| – |Vt| |
V
OC
|VOS| |VOS|
∆|VOC| |VOS – VOS| |VOS – VOS|
I
OS
|Isa|, |Isb|
I
O
|Ixa|, |Ixb| Iia, I
ib
RECEIVER SECTIONS
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IT+
Positive-going input threshold voltage VO = 2.7 V, IO = –0.4 mA 0.2 V
V
IT–
Negative-going input threshold voltage VO = 0.5 V, IO = 16 mA
–0.2
‡
V
V
hys
Input hysteresis voltage (V
IT+
– V
IT–
) 50 mV
V
IK
Enable clamp voltage SN751177 II = –18 mA –1.5 V
V
OH
High-level output voltage VID = 200 mV , IOH = –400 µA 2.7 V
p
IOL = 8 mA 0.45
VOLLow-level output voltage
V
ID
= –
200 mV
IOL = 16 mA 0.5
V
I
OZ
High-impedance-state output current SN751177 VO = 0.4 V to 2.4 V ±20 µA
p
p
VI = 12 V 1
IILine input current (see Note 7)
Other input at 0 V
VI = –7 V –0.8
mA
I
IH
High-level enable input current SN751177 VIH = 2.7 V 20 µA
I
IL
Low-level enable input current SN751177 VIL = 0.4 V –100 µA
I
OS
Short-circuit output current (see Note 6) –15 –85 µA
I
CC
Supply current No load, Outputs enabled 80 110 mA
r
i
Input resistance 12 kΩ
†
All typical values are at VCC = 5 V and TA = 25°C.
‡
The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode
output and threshold voltage levels only .
NOTES: 6. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
7. Refer to ANSI Standards TIA/EIA-422-B, TIA/EIA-423-A, and TIA/EIA-485-A for exact conditions.
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUARY 1990 – REVISED MAY 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics at VCC = 5 V, CL = 15 pF, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low- to high-level output
20 35 ns
t
PHL
Propagation delay time, high- to low-level output
V
ID
= –1.5 V to 1.5 V,
See Figure 7
22 35 ns
t
PZH
Output enable time to high level 17 25 ns
t
PZL
Output enable time to low level
20 27 ns
t
PHZ
Output disable time from high level
SN751177
See Figure 8
25 40 ns
t
PLZ
Output disable time from low level 30 40 ns
PARAMETER MEASUREMENT INFORMATION
V
OC
V
OD2
R
L
2
R
L
2
Figure 1. Driver Test Circuit, VOD and V
OC
V
OL
V
OH
–I
OH
+I
OL
V
ID
Figure 2. Receiver Test Circuit, VOH and V
OL
TEST CIRCUIT
50 Ω
3 V
Output
RL = 54 Ω
Generator
(see Note B)
CL = 50 pF
(see Note A)
VOLTAGE WAVEFORMS
Output
Input
t
d(OD)
t
d(OD)
t
t(OD)
t
t(OD)
≈ 2.5 V
0 V
3 V
≈ –2.5 V
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.
1.5 V 1.5 V
90% 90%
50%
10%
50%
10%
Figure 3. Driver Differential Output-Delay and Transition-Time Test Circuit and Voltage Waveforms
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUARY 1990 – REVISED MAY 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Y
Output
V
OL
V
OH
V
OL
V
OH
t
PLH
t
PHL
t
PHL
t
PLH
Output
RL = 27 Ω
VOLTAGE WAVEFORMSTEST CIRCUIT
50 Ω
Input
0 V
3 V
Generator
(see Note B)
CL = 15 pF
(see Note A)
Z
Output
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.
1.5 V 1.5 V
2.3 V 2.3 V
2.3 V 2.3 V
3 V
2.3 V
S1
Figure 4. Driver Propagation-Time Test Circuit and Voltage Waveforms
t
PHZ
V
off
≈ 0 V
Output
V
OH
VOLTAGE WAVEFORMSTEST CIRCUIT
Input
0 V
3 V
t
PZH
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.
RL = 110 Ω
50 Ω
Generator
(see Note B)
CL = 15 pF
(see Note A)
0 V or 3 V
Output
1.5 V 1.5 V
0.5 V
2.3 V
S1
Figure 5. Driver Enable- and Disable-Time Test Circuit and Voltage Waveforms
V
OL
5 V
t
PLZ
t
PZL
Output
VOLTAGE WAVEFORMSTEST CIRCUIT
Input
0 V
3 V
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.
RL = 110 Ω
50 Ω
Generator
(see Note B)
CL = 15 pF
(see Note A)
0 V or 3 V
S1
Output
5 V
0.5 V
1.5 V
2.3 V
1.5 V
Figure 6. Driver Enable- and Disable-Time Test Circuit and Voltage Waveforms
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUARY 1990 – REVISED MAY 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
OL
V
OH
t
PHL
t
PLH
Output
VOLTAGE WAVEFORMSTEST CIRCUIT
50 Ω
Output
Input
0 V
3 V
Generator
(see Note B)
CL = 15 pF
(see Note A)
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.
1.5 V 0 V
1.5 V 1.5 V
1.3 V 1.3 V
Figure 7. Receiver Propagation-Time Test Circuit and Voltage Waveforms
VOLTAGE WAVEFORMS
≈ 1.3 V
0.5 V
t
PHZ
3 V
0 V
V
OH
Input
Output
0 V
3 V
V
OL
S1 to –1.5 V
S2 Closed
S3 Open
V
OL
1.5 V
≈ 4.5 V
t
PZL
3 V
1.5 V
0 V
Output
Input
t
PZH
0 V
V
OH
0 V
1.5 V
3 V
1.5 V
TEST CIRCUIT
1N916 or Equivalent
2 kΩ
5 kΩ
50 Ω
≈ 1.3 V
t
PLZ
S1 to –1.5 V
S2 Closed
S3 Closed
S1 to 1.5 V
S2 Closed
S3 Closed
Generator
(see Note B)
CL = 15 pF
(see Note A)
Input
Output
Output
Input
S1 to 1.5 V
S3 Closed
S2 Open
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.
5 V
S3
1.5 V
–1.5 V
S1
S2
0.5 V
1.5 V
1.5 V
Figure 8. Receiver Output Enable- and Disable-Time Test Circuit and Voltage Waveforms
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 1999, Texas Instruments Incorporated
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