TEXAS INSTRUMENTS SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680 Technical data
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D
Choice of Memory Organizations
– SN74V3640 – 1024 × 36 Bit
– SN74V3650 – 2048 × 36 Bit
– SN74V3660 – 4096 × 36 Bit
– SN74V3670 – 8192 × 36 Bit
– SN74V3680 – 16384 × 36 Bit
– SN74V3690 – 32768 × 36 Bit
D
166-MHz Operation (6-ns Read/Write Cycle
Time)
D
User-Selectable Input- and Output-Port Bus
Sizing
– ×36 in to ×36 out
– ×36 in to ×18 out
– ×36 in to ×9 out
– ×18 in to ×36 out
– ×9 in to ×36 out
D
Big-Endian/Little-Endian User-Selectable
Byte Representation
D
5-V-Tolerant Inputs
D
Fixed, Low, First-Word Latency
D
Zero-Latency Retransmit
D
Master Reset Clears Entire FIFO
D
Partial Reset Clears Data, But Retains
Programmable Settings
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
D
Empty, Full, and Half-Full Flags Signal FIFO
Status
D
Programmable Almost-Empty and
Almost-Full Flags; Each Flag Can Default to
One of Eight Preselected Offsets
D
Selectable Synchronous/Asynchronous
Timing Modes for Almost-Empty and
Almost-Full Flags
D
Program Programmable Flags by Either
Serial or Parallel Means
D
Select Standard Timing (Using EF and FF
Flags) or First-Word Fall-Through (FWFT)
Timing (Using OR
D
Output Enable Puts Data Outputs in
High-Impedance State
D
Easily Expandable in Depth and Width
D
Independent Read and Write Clocks Permit
Reading and Writing Simultaneously
D
High-Performance Submicron CMOS
Technology
D
Available in 128-Pin Thin Quad Flat Pack
(TQFP)
and IR Flags)
description
The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally
deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible
bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits:
D
Flexible ×36/×18/×9 bus matching on both read and write ports
D
The period required by the retransmit operation is fixed and short.
D
The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can
be read, is fixed and short.
D
High-density offerings up to 1 Mbit
Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing,
telecommunications, data communications, and other applications that need to buffer large amounts of data
and match buses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or
9-bit width, as determined by the state of external control pins’ input width (IW), output width (OW), and bus
matching (BM) during the master-reset cycle.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
1
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
PEU PACKAGE
(TOP VIEW)
WEN
SEN
DNC
V
CC
DNC
IW
D35
D34
D33
D32
V
CC
D31
D30
GND
D29
D28
D27
D26
D25
D24
D23
GND
D22
V
CC
D21
D20
D19
D18
GND
D17
D16
D15
D14
D13
V
CC
D12
GND
D11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
PRS
WCLK
127
128
40
39
MRS
126
41
FWFT/SI
LD
124
125
43
42
V
FF/IR
122
123
44
CC
45
PAF
121
46
GND
120
47
OW
119
48
HF
FSEL0
117
118
50
49
GND
116
51
FSEL1
BE
114
115
53
52
CC
V
IP
BM
PAE
111
110
112
113
57
56
55
54
PFM
109
58
RM
EF/OR
107
108
60
59
GND
106
61
RCLK
REN
104
105
63
62
RT
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
OE
V
CC
V
CC
Q35
Q34
Q33
Q32
GND
GND
Q31
Q30
Q29
Q28
Q27
Q26
V
CC
Q25
Q24
GND
GND
Q23
Q22
Q21
Q20
Q19
Q18
GND
Q17
Q16
V
CC
V
CC
Q15
Q14
Q13
Q12
GND
Q11
Q10
D9
D7
D6
D10
D8
D5D4D3
GND
V
CC
D2D1D0
GND
Q0
Q1
Q2
Q3Q4Q5
GND
Q6
V
CC
Q7
Q8
Q9
DNC = Do not connect
description (continued)
The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO
on every rising edge of WCLK when WEN
read-enable (REN
An output-enable (OE
2
) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted.
) input is provided for 3-state control of the outputs.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
is asserted. The output port is controlled by read-clock (RCLK) and
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
functional block diagram
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
WCLK
WEN
BE
BM
IW
OW
MRS
PRS
D0–Dn (×36, ×18, or ×9)
128
1
Write-Control
Logic
Write
Pointer
16384 × 36, 32768 × 36
114
113
IP
112
6
119
126
127
Control
Logic
Bus
Configuration
Reset
Logic
102
OE
Q0–Qn (×36, ×18, or ×9)
Input
Register
RAM Array
1024 × 36, 2048 × 36,
4096 × 36, 8192 × 36,
Output
Register
SEN
LD
125
Offset
Register
Flag
Logic
Read
Pointer
Read-Control
Logic
105 104
2
123
FF/IR
121
PAF
108
EF/OR
110
PAE
117
HF
124
FWFT/SI
109
PFM
118
FSEL0
115
FSEL1
103
RT
107
RM
RENRCLK
description (continued)
The frequencies of the RCLK and WCLK signals can vary from 0 to f
are no restrictions on the frequency of one clock input with respect to the other.
There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and
standard mode.
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three
transitions of the RCLK signal. REN need not be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a low on REN
for access. The state of the FWFT/SI input during master
reset determines the timing mode.
For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode
permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a
specific read operation is performed. A read operation, which consists of activating REN
RCLK edge, shifts the word from internal memory to the data output lines.
, with complete independence. There
MAX
and enabling a rising
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
Partial Reset (PRS)
Write Clock (WCLK)
Write Enable (WEN
Load (LD
(×36, ×18, ×9) Data In (D0–Dn)
Serial Enable (SEN
First-Word Fall-Through or Serial Input
Full Flag or Input Ready (FF
Programmable Almost-Full Flag (PAF
(FWFT/SI)
/IR)
Input Width (IW)
Figure 1. Single-Device-Configuration Signal Flow
Master Reset (MRS)
Read Clock (RCLK)
)
)
SN74V3640
)
)
SN74V3650
SN74V3660
SN74V3670
SN74V3680
SN74V3690
Bus
Matching
(BM)
Output Width (OW)
Read Enable (REN)
Output Enable (OE
(×36, ×18, ×9) Data Out (Q0–Qn)
Retransmit (RT
Empty Flag or Output Ready (EF/OR)
Programmable Almost-Empty Flag (PAE
Half-Full Flag (HF
Big Endian/Little Endian (BE
Interspersed/
Noninterspersed Parity (IP)
)
)
)
)
)
description (continued)
These FIFOs have five flag pins: empty flag or output ready (EF/OR), full flag or input ready (FF/IR), half-full
flag (HF
functions are selected in standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE, and
PAF
PAE
determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset
settings also are provided, so that P AE
boundary. The PAF
offset values are set during master reset by the state of the FSEL0, FSEL1, and LD
For serial programming, SEN
edge of WCLK. For parallel programming, WEN
rising edge of WCLK. REN
RCLK, regardless of whether serial parallel offset loading has been selected.
During master reset (MRS
selects standard mode or FWFT mode.
Partial reset (PRS
mode, programmable-flag programming method, and default or programmed offset settings existing before
partial reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS
is useful for resetting a device in mid-operation, when reprogramming programmable flags would be
undesirable.
Also, the timing modes of PAE
asynchronous or synchronous for PAE
), programmable almost-empty flag (PAE), and programmable almost-full flag (PAF). The EF and FF
always are available for use, regardless of timing mode.
and PAF can be programmed independently to switch at any point in memory. Programmable offsets
can be set to switch at a predefined number of locations from the empty
threshold also can be set at similar predefined values from the full boundary. The default
.
, together with LD, loads the offset registers via the serial input (SI) on each rising
, together with LD, loads the offset registers via Dn on each
, together with LD, can read the offsets in parallel from Qn on each rising edge of
), the read and write pointers are set to the first location of the FIFO. The FWFT pin
) also sets the read and write pointers to the first location of the memory . However, the timing
and PAF outputs can be selected. Timing modes can be set as either
and PAF.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
description (continued)
If the asynchronous PAE/PAF configuration is selected, PAE is asserted low on the low-to-high transition of
RCLK. PAE
low-to-high transition of WCLK, and PAF
If the synchronous P AE/PAF configuration is selected , the PAE is asserted and updated on the rising edge of
RCLK only, and not WCLK. Similarly, PAF
RCLK. The mode desired is configured during master reset by the state of the programmable flag mode (PFM).
is reset to high on the low-to-high transition of WCLK. Similarly, PAF is asserted low on the
is reset to high on the low-to-high transition of RCLK.
is asserted and updated on the rising edge of WCLK only, and not
The retransmit function allows data to be reread from the FIFO more than once. A low on the retransmit (RT
input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location
of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode
(RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset
selects normal latency.
If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output
register, with respect to the same RCLK edge that initiated the retransmit, if RT
is low.
See Figures 1 1 and 12 for normal latency retransmit timing. See Figures 13 and 14 for zero-latency retransmit
timing.
The devices can be configured with different input and output bus widths (see Table 1).
Table 1. Bus-Matching Configuration Modes
BM IW OW
L L L ×36 ×36
H L L ×36 ×18
H L H ×36 ×9
H H L ×18 ×36
H H H ×9 ×36
†
Logic levels during master reset
WRITE-PORT
WIDTH
READ-PORT
WIDTH
†
A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO
in long-word (×36/×18) format and read out of the FIFO in small-word (×18/×9) format. If big-endian mode is
selected, the most-significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO
first, followed by the least-significant byte (LSB). If little-endian format is selected, the LSB of the long word
written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset
by the state of the big-endian/little-endian (BE
) pin (see Figure 4 for the bus-matching byte arrangement).
)
The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded
into the parallel port (D0–Dn) when programming the flag offsets. If interspersed-parity mode is selected, the
FIFO assumes that the parity bit is located in bit positions D8, D17, D26, and D35 during the parallel
programming of the flag offsets. If noninterspersed-parity mode is selected, D8, D17, and D26 are assumed
to be valid bits, and D32, D33, D34, and D35 are ignored. Interspersed parity mode is selected during master
reset by the state of the IP input. Interspersed parity control has an effect only during parallel programming of
the offset registers. It does not affect data written to and read from the FIFO.
The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are fabricated using
high-speed submicron CMOS technology, and are characterized for operation from 0°C to 70°C.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
Terminal Functions
TERMINAL
NAME
†
BE
†
BM
D0–D36 I
EF/OR O
FF/IR O
†
FSEL0
†
FSEL1
FWFT/SI I
HF O Half-full flag. HF indicates whether the FIFO memory is more or less than half full.
†
IP
†
IW
LD I
MRS I
OE I Output enable. OE controls the output impedance of Qn.
†
OW
PAE O
PAF O
†
PFM
PRS I
Q0–Q35 O
RCLK I
†
Inputs should not change state after master reset.
I/O DESCRIPTION
Big endian/little endian. During master reset, a low on BE selects big-endian operation. A high on BE during master
I
reset selects little-endian format.
Bus matching. BM works with IW and OW to select the bus sizes for both write and read ports (see T able 1 for bus-size
I
configuration).
Data inputs. Data inputs for a 36-, 18-, or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a
don’t-care state.
Empty flag/output ready. In standard mode, the EF function is selected. EF indicates whether the FIFO memory is
empty. In FWFT mode, the OR
Full flag/input ready . In standard mode, the FF function is selected. FF indicates whether the FIFO memory is full. In
FWFT mode, the IR
Flag-select bit 0. During master reset, FSEL0, along with FSEL1 and LD, selects the default offset values for PAE and
I
PAF
. Up to eight possible settings are available.
Flag-select bit 1. During master reset, FSEL1, along with FSEL0 and LD, selects the default offset values for PAE and
I
PAF
. Up to eight possible settings are available.
First-word fall-through/serial in. During master reset, FWFT/SI selects FWFT or standard mode. After master reset,
FWFT/SI functions as a serial input for loading offset registers.
Interspersed parity. During master reset, a low on IP selects noninterspersed-parity mode. A high selects
interspersed-parity mode. Interspersed-parity control has an effect only during parallel programming of the offset
I
registers. It does not effect data written to and read from the FIFO.
I Input width. IW, along with OW and BM, selects the bus width of the write port (see Table 1 for bus-size configuration).
Load. This is a dual-purpose pin. During master reset, the state of LD, along with FSEL0 and FSEL1, determines one
of eight default offset values for PAE
programmed, parallel or serial (see Table 2). After master reset, LD
registers.
Master reset. MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
master reset, the FIFO is configured for either FWFT or standard mode, bus-matching configurations, one of eight
programmable-flag default settings, serial or parallel programming of the offset settings, big-endian/little-endian
format, zero-latency timing mode, interspersed parity, and synchronous versus asynchronous programmable-flag
timing modes.
I Output width. OW, along with IW and BM, selects the bus width of the read port (see T able 1 for bus-size configuration).
Programmable almost-empty flag. PAE goes low if the number of words in the FIFO memory is less than of fset n, which
is stored in the empty offset register. PAE
equal to, offset n.
Programmable almost-full flag. PAF goes high if the number of free locations in the FIFO memory is more than
offset m, which is stored in the full offset register. PAF
is less than, or equal to, m.
Programmable-flag mode. During master reset, a low on PFM selects asynchronous programmable-flag timing mode.
I
A high on PFM selects synchronous programmable-flag timing mode.
Partial reset. PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During partial
reset, the existing mode (standard or FWFT), programming method (serial or parallel), and programmable-flag
settings are all retained.
Data outputs. Data outputs for a 36-, 18-, or 9-bit bus. When in 18- or 9-bit mode, the unused output pins are in a
don’t-care state. Outputs are not 5-V tolerant, regardless of the state of OE
Read clock. When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from the
programmable registers.
function is selected. IR indicates whether there is space available for writing to the FIFO memory.
function is selected. OR indicates whether there is valid data available at the outputs.
and PAF, along with the method by which these offset registers can be
enables writing to and reading from the offset
goes high if the number of words in the FIFO memory is greater than, or
goes low if the number of free locations in the FIFO memory
.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
Terminal Functions (Continued)
TERMINAL
NAME
REN I Read enable. REN enables RCLK for reading data from the FIFO memory and offset registers.
†
RM
RT I
SEN I Serial enable. SEN enables serial loading of programmable flag offsets.
WCLK I
WEN I Write enable. WEN enables WCLK for writing data into the FIFO memory and offset registers.
†
Inputs should not change state after master reset.
I/O DESCRIPTION
Retransmit latency mode. During master reset, a low on RM selects zero-latency retransmit timing mode. A high on
I
RM selects normal-latency mode.
Retransmit. RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to low (OR
to high in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode, or
programmable-flag settings. RT
Write clock. When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the
programmable registers for parallel programming and, when enabled by SEN
of data into the programmable register for serial programming.
is useful to reread data from the first physical location of the FIFO.
, the rising edge of WCLK writes one bit
detailed description
inputs
data in (D0–Dn)
D0–D35 are data inputs for 36-bit-wide data. D0–D17 are data inputs for 18-bit-wide data. D0–D8 are data
inputs for 9-bit-wide data.
controls
master reset (MRS
A master reset is accomplished when MRS
to the first location of the RAM array. PAE
)
is taken low. This operation sets the internal read and write pointers
goes low, PAF goes high, and HF goes high.
If FWFT/SI is low during master reset, the standard mode, EF
high. If FWFT/SI is high, the FWFT mode, IR
All control settings, such as OW, IW, BM, BE
, and OR are selected. OR goes high and IR goes low.
, RM, PFM, and IP are defined during the master reset cycle.
, and FF are selected. EF goes low and FF goes
During a master reset, the output register is initialized to all zeroes. A master reset is required after power up,
before a write operation can take place. MRS
is asynchronous.
See Figure 5 for timing information.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
partial reset (PRS)
A partial reset is accomplished when the PRS
the internal read and write pointers are set to the first location of the RAM array , P AE
and HF
Whichever mode is active at the time of partial reset remains selected (standard or FWFT mode). If standard
mode is active, FF
Following partial reset, all values held in the offset registers remain unchanged. The programming method
(parallel or serial) active at the time of partial reset also is retained. The output register is initialized to all zeroes.
PRS
A partial reset is useful for resetting the device during operation when reprogramming programmable-flag
offsets might not be convenient.
See Figure 6 for timing information.
goes high.
goes high and EF goes low. If the FWFT mode is active, OR goes high and IR goes low.
is asynchronous.
input is taken to a low state. As in the case of the master reset,
goes low, PAF goes high,
retransmit (RT
The retransmit operation allows previously read data to be accessed again. There are two modes of retransmit
operation: normal latency and zero latency. There are two stages to retransmit. The first stage is a setup
procedure that resets the read pointer to the first location of memory . The second stage is the actual retransmit,
which consists of reading out the memory contents, starting at the beginning of the memory.
Retransmit setup is initiated by holding RT
bringing RT
If standard mode is selected, the FIFO marks the beginning of the retransmit setup by setting EF
change in level is noticeable only if EF
initialized to the first location of the RAM array.
When EF
in memory . Because standard mode is selected, every word read, including the first word following retransmit
setup, requires a low on REN
See Figure 11 for timing information.
If FWFT mode is selected, the FIFO marks the beginning of the retransmit setup by setting OR
period, the internal read pointer is set to the first location of the RAM array.
When OR
the outputs. Because FWFT mode is selected, the first word appears on the outputs and no low on REN
necessary. Reading all subsequent words requires a low on REN
See Figure 12 for timing information.
)
low during a rising RCLK edge. REN and WEN must be high before
low. When zero latency is utilized, REN need not be high before bringing RT low.
was high before setup. During this period, the internal read pointer is
goes high, retransmit setup is complete and read operations can begin, starting with the first location
to enable the rising edge of RCLK.
high. During this
goes low, retransmit setup is complete. At the same time, the contents of the first location appear on
to enable the rising edge of RCLK.
low. The
is
In retransmit operation, zero-latency mode can be selected using the retransmit latency mode (RM) pin during
a master reset. This can be applied to the standard mode and the FWFT mode.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
first-word fall-through/serial in (FWFT/SI)
FWFT/SI is a dual-purpose pin. During master reset, the state of the FWFT/SI input determines whether the
device operates in standard or FWFT mode.
If, at the time of master reset, FWFT/SI is low, standard mode is selected. This mode uses EF
any words are present in the FIFO memory . It also uses FF
for writing. In standard mode, every word read from the FIFO, including the first, must be requested using REN
and RCLK.
If, at the time of master reset, FWFT/SI is high, FWFT mode is selected. This mode uses OR
there is valid data at the data outputs (Qn). It also uses IR
for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising
edges, therefore, REN
After master reset, FWFT/SI acts as a serial input for loading PAE
registers. The serial input function can be used only when the serial loading method is selected during master
reset. Serial programming using the FWFT/SI pin functions the same way in both standard and FWFT modes.
write clock (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data setup and hold times must be met, with
respect to the low-to-high transition of the WCLK. It is permissible to stop WCLK. Note that while WCLK is idle,
the FF
/IR, P AF, and HF flags are not updated. WCLK is capable only of updating HF flag to low . The write and
read clocks can be independent or coincident.
write enable (WEN
When WEN
device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation.
When WEN
T o prevent data overflow in the standard mode, FF
of a valid read cycle, FF
RCLK cycle.
)
is low, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the
is high, no new data is written in the RAM array on each WCLK cycle.
= low is not necessary. Subsequent words must be accessed using REN and RCLK.
goes low, inhibiting further write operations. After completion
goes high, allowing a write to occur. FF is updated by two WCLK cycles + tsk after the
to indicate whether the FIFO memory has free space
to indicate whether the FIFO memory has free space
and PAF offsets into the programmable
to indicate whether
to indicate whether
To prevent data overflow in the FWFT mode, IR
of a valid read cycle, IR
after the valid RCLK cycle.
is ignored when the FIFO is full in either FWFT or standard mode.
WEN
read clock (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can be read on the outputs, on the rising edge
of the RCLK input. It is permissible to stop RCLK. While RCLK is idle, the EF
updated. RCLK is capable only of updating the HF
or coincident.
goes low, allowing a write to occur. The IR flag is updated by two WCLK cycles + t
goes high, inhibiting further write operations. After completion
/OR, PAE, and HF flags are not
flag to high. The write and read clocks can be independent
sk
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
read enable (REN)
When REN
cycle, if the device is not empty.
is low, data is loaded from the RAM array into the output register on the rising edge of every RCLK
When REN
The data outputs Q0–Qn maintain the previous data value.
In standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be
requested using REN. When the last word has been read from the FIFO, the empty flag (EF) goes low, inhibiting
further read operations. REN
allowing a read to occur. The EF
In FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third valid
low-to-high transition of RCLK + t
other words, a read must be executed using REN
read from the FIFO and OR
REN
serial enable (SEN
The SEN
method must be selected during master reset. SEN
at the SI input can be loaded into the program register, with one bit for each low-to-high transition of WCLK.
When SEN
functions the same way in standard and FWFT modes.
output enable (OE
When output enable is asserted (low), the parallel output buffers receive data from the output register. When
is high, the output data bus (Qn) goes into the high-impedance state.
OE
load (LD
)
LD
is a dual-purpose pin. During master reset, the state of the LD input, along with FSEL0 and FSEL1,
determines one of eight default offset values for the P AE
offset registers can be programmed, parallel or serial (see Table 2). After master reset, LD
operations to, and read operations from, the offset registers. Only the offset loading method currently selected
can be used to write to the registers. Offset registers can be read only in parallel.
is high, the output register holds the previous data and no new data is loaded into the output register.
is ignored when the FIFO is empty. Once a write is performed, EF goes high,
flag is updated by two RCLK cycles + tsk after the valid WCLK cycle.
after the first write. REN need not be asserted low. In order to access all
sk
goes high with a true read (RCLK with REN = low), inhibiting further read operations.
is ignored when the FIFO is empty.
)
input is an enable used only for serial programming of the offset registers. The serial programming
is high, the programmable registers retain the previous settings and no offsets are loaded. SEN
)
. The RCLK low-to-high transition after the last word has been
always is used with LD. When these lines are both low, data
and P AF flags, along with the method by which these
enables write
After master reset, LD
begins a serial loading, or a parallel load, or a read of these offset values.
bus matching (BM, IW, OW)
BM, IW, and OW define the input and output bus widths. During master reset, the state of these pins is used
to configure the device bus sizes (see Table 1 for control settings). All flags operate on the word/byte-size
boundary, as defined by the selection of bus width (see Figure 4 for the bus-matching byte arrangement).
big endian/little endian (BE
During master reset, a low on BE
little-endian format. This function is useful when the following input-to-output bus widths are implemented: ×36
to ×18, ×36 to ×9, ×18 to ×36, and ×9 to ×36. If big-endian mode is selected, the MSB (word) of the long word
written into the FIFO is read out of the FIFO first, followed by the LSB. If little-endian format is selected, the LSB
of the long word written into the FIFO is read out first, followed by the MSB. The desired mode is configured
during master reset by the state of BE
10
activates the programming process of the flag offset values P AE and P AF . Pulling LD low
)
selects big-endian operation. A high on BE during master reset selects
(see Figure 4 for bus-matching byte arrangement).
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
programmable-flag mode (PFM)
During master reset, a low on PFM selects asynchronous programmable-flag timing mode. A high on PFM
selects synchronous programmable-flag timing mode. If asynchronous PAF
(PFM low during MRS
low-to-high transition of WCLK. Similarly , PAF
is reset to high on the low-to-high transition of RCLK.
), P AE is asserted low on the low-to-high transition of RCLK. PAE is reset to high on the
is asserted low on the low-to-high transition of WCLK, and P AF
/PAE configuration is selected
If synchronous P AE
rising edge of RCLK only , and not WCLK. Similarly, P AF
only and not RCLK. The mode desired is configured during master reset by the state of the PFM.
interspersed parity (IP)
During master reset, a low on IP selects noninterspersed-parity mode. A high selects interspersed-parity mode.
The IP bit function allows the user to select the parity bit in the word loaded into the parallel port (D0–Dn) when
programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bits are
located in bit positions D8, D17, D26, and D35 during the parallel programming of the flag offsets. If
noninterspersed-parity mode is selected, D8, D17, and D28 are assumed to be valid bits and D32, D33, D34,
and D35 are ignored. IP mode is selected during master reset by the state of the IP input pin. Interspersed-parity
control has an effect only during parallel programming of the offset registers. It does not affect the data written
to, and read from, the FIFO.
outputs
full flag/input ready (FF
FF
/IR is a dual-purpose pin. In standard mode, the FF function is selected. When the FIFO is full, FF goes low,
inhibiting further write operations. When FF
(either MRS
SN74V3650, D = 4096 for the SN74V3660, D = 8192 for the SN74V3670, D = 16384 for the SN74V3680, and
D = 32768 for the SN74V3690).
See Figure 7 for timing information.
In FWFT mode, the IR function is selected. IR goes low when memory space is available for writing in data.
When there is no longer any free space left, IR
performed after a reset (either MRS
SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the SN74V3660, D = 8193 for the
SN74V3670, D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690).
or PRS), FF goes low after D writes to the FIFO (D = 1024 for the SN74V3640, D = 2048 for the
/PAF configuration is selected (PFM high during MRS), PAE is asserted and updated on the
is asserted and updated on the rising edge of WCLK
/IR)
is high, the FIFO is not full. If no reads are performed after a reset
goes high, inhibiting further write operations. If no reads are
or PRS), IR goes high after D writes to the FIFO (D = 1025 for the
See Figure 9 for timing information.
status not only measures the contents of the FIFO memory , but also counts the presence of a word in
The IR
the output register. Thus, in FWFT mode, the total number of writes necessary to deassert IR
needed to assert FF
/IR is synchronous and updated on the rising edge of WCLK. FF/IR are double register-buffered outputs.
FF
in standard mode.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
is one greater than
11
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
empty flag/output ready (EF/OR)
EF
/OR is a dual-purpose pin. In the standard mode, the EF function is selected. When the FIFO is empty , EF
goes low, inhibiting further read operations. When EF is high, the FIFO is not empty.
See Figure 8 for timing information.
In FWFT mode, the OR
FIFO appears valid on the outputs. OR
from the FIFO memory to the outputs. OR
data stays at the outputs, indicating the last word was read. Further data reads are inhibited until OR
again.
See Figure 10 for timing information.
/OR is synchronous and updated on the rising edge of RCLK.
EF
In standard mode, EF
output.
programmable almost-full flag (PAF
PAF
goes low when the FIFO reaches the almost-full condition. In standard mode, if no reads are performed
after reset (MRS
writes for the SN74V3640, (2048 – m) writes for the SN74V3650, (4096 – m) writes for the SN74V3660,
(8192 – m) writes for the SN74V3670, (16384 – m) writes for the SN74V3680, and (32768 – m) writes for the
SN74V3690. The offset m is the full offset value. The default setting for this value is shown in Table 2.
In FWFT mode, P AF
(4097 – m) writes for the SN74V3660, (8193 – m) writes for the SN74V3670, (16385 – m) writes for the
SN74V3680, and (32769 – m) writes for the SN74V3690. The offset m is the full offset value. The default setting
for this value is shown in Table 2.
See Figure 18 for timing information.
If the asynchronous P AF
PAF
is reset to high on the low-to-high transition of RCLK. If the synchronous P AF configuration is selected, PAF
is updated on the rising edge of WCLK.
), P AF goes low after (D – m) words are written to the FIFO. The P AF goes low after (1024 – m)
function is selected. OR goes low at the same time the first word written to an empty
stays low after the RCLK low-to-high transition that shifts the last word
goes high only with a true read (RCLK with REN = low). The previous
is a double register-buffered output. In FWFT mode, OR is a triple register-buffered
)
goes low after (1025 – m) writes for the SN74V3640, (2049 – m) writes for the SN74V3650,
configuration is selected, P AF is asserted low on the low-to-high transition of WCLK.
goes low
See Figure 20 for timing information.
programmable almost-empty flag (PAE
PAE
goes low when the FIFO reaches the almost-empty condition. In standard mode, P AE goes low when there
are n words, or fewer, in the FIFO. The offset n is the empty offset value. The default setting for this value is
shown in Table 2.
In FWFT mode, PAE
value is shown in Table 2.
See Figure 19 for timing information.
If the asynchronous P AE
PAE
is reset to high on the low-to-high transition of WCLK. If the synchronous PAE configuration is selected,
PAE
is updated on the rising edge of RCLK.
See Figure 21 for timing information.
goes low when there are n + 1 words, or fewer, in the FIFO. The default setting for this
configuration is selected, P AE is asserted low on the low-to-high transition of RCLK.
)
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
half-full flag (HF)
HF
indicates a half-full FIFO. The rising WCLK edge that fills the FIFO beyond half-full sets HF low. The flag
remains low until the difference between the write and read pointers becomes less than, or equal to, one-half
of the total depth of the device. The rising RCLK edge that accomplishes this condition sets HF
In standard mode, if no reads are performed after reset (MRS or PRS), HF goes low after (D/2 + 1) writes to
the FIFO, where D = 1024 for the SN74V3640, D = 2048 for the SN74V3650, D = 4096 for the SN74V3660,
D = 8192 for the SN74V3670, D = 16384 for the SN74V3680, and D = 32768 for the SN74V3690.
high.
In FWFT mode, if no reads are performed after reset (MRS
to the FIFO, where D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the SN74V3660,
D = 8193 for the SN74V3670, D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690.
See Figure 22 for timing information. Because HF is updated by both RCLK WCLK, it is considered
asynchronous.
data outputs (Q0-Qn)
Q0–Q35 are data outputs for 36-bit-wide data. Q0–Q17 are data outputs for 18-bit-wide data. Q0–Q8 are data
outputs for 9-bit-wide data.
or PRS), HF goes low after [(D – 1)/2] + 2 writes
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Continuous output current, I
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
–0.5 V to 4.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
MIN TYP MAX UNIT
V
Supply voltage (see Note 1) 3.15 3.3 3.45 V
CC
GND Supply voltage 0 0 0 V
V
High-level input voltage (see Note 2) 2 5.5 V
IH
V
Low-level input voltage (see Note 3) 0.8 V
IL
T
Operating free-air temperature 0 70 °C
A
NOTES: 1. VCC = 3.3 V ± 0.15 V, JEDEC JESD8-A compliant
electrical characteristics over recommended operating conditions, t
2. Outputs are not 5-V tolerant.
3. 1.5-V undershoots are allowed for 10 ns once per cycle.
= 6 ns, 7.5 ns, 10 ns, and
CLK
15 ns (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
V
OL
I
I
I
OZ
I
CC1
I
CC2
C
IN
C
OUT
NOTES: 4. Tested with outputs open (I
5. RCLK and WCLK switch at 20 MHz and data inputs switch at 10 MHz.
6. Typical I
using TTL levels), data switching at fS/2, CL = capacitive load (in pF)
7. All inputs = (VCC – 0.2 V) or (GND + 0.2 V), except RCLK and WCLK, TA = 25°C, which switch at 20 MHz.
IOH = –2 mA 2.4 V
IOL = 8 mA
VI = VCC to 0.4 V ±1 µA
OE ≥ VIH, VO = VCC to 0.4 V ±10 µA
See Notes 4, 5, and 6 40 mA
See Notes 4 and 7 15 mA
VI = 0, TA = 25°C, f = 1 MHz 10 pF
VO = 0, TA = 25°C, f = 1 MHz, Output deselected (OE ≥ VIH) 10 pF
= 0)
OUT
= 4.2 + 1.4 ×fS + 0.02 ×CL × fS (in mA), with VCC = 3.3 V , TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz,
CC1
0.4 V
†
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2 through Figure 22)
f
clock
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
LDS
t
LDH
t
RS
t
RSS
t
RSR
t
RSF
t
RTS
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAFA
t
PAFS
t
PAEA
t
PAES
t
HF
t
sk1
t
sk2
†
All ac timings apply to standard mode and FWFT mode.
‡
Pulse durations less than minimum values are not allowed.
Clock cycle frequency 166 133.3 100 66.7 MHz
Data access time 2 4.5 2 5 2 6.5 2 10 ns
Clock cycle time 6 7.5 10 15 ns
Clock high time 2.5 3.5 4.5 6 ns
Clock low time 2.5 3.5 4.5 6 ns
Data setup time 1.5 2.5 3.5 4 ns
Data hold time 0.5 0.5 0.5 1 ns
Enable setup time 1.5 2.5 3.5 4 ns
Enable hold time 0.5 0.5 0.5 1 ns
Load setup time 2 3.5 3.5 4 ns
Load hold time 0 0.5 0.5 1 ns
Reset pulse duration
Reset setup time 15 15 15 15 ns
Reset recovery time 10 10 10 15 ns
Reset to flag and output time 15 15 15 15 ns
Retransmit setup time 2 3.5 3.5 4 ns
Output enable to output in low impedance 0 0 0 0 ns
Output enable to output valid 2 4.5 2 6 2 6 2 8 ns
Output enable to output in high impedance 2 4.5 2 6 2 6 2 8 ns
Write clock to FF or IR 4.5 5 6.5 10 ns
Read clock to EF or OR 4.5 5 6.5 10 ns
Clock to asynchronous PAF 8.5 12.5 16 20 ns
Write clock to synchronous PAF 4.5 5 6.5 10 ns
Clock to asynchronous PAE 8.5 12.5 16 20 ns
Read clock to synchronous PAE 4.5 5 6.5 10 ns
Clock to HF 9 12.5 16 20 ns
Skew time between read clock and
write clock for EF
Skew time between read clock and
write clock for PAE
‡
/OR and FF/IR
and PAF
†
SN74V3640-6
SN74V3650-6
SN74V3660-6
SN74V3670-6
SN74V3680-6
SN74V3690-6
MIN MAX MIN MAX MIN MAX MIN MAX
10 10 10 15 ns
4.5 5 7 9 ns
4.5 7 10 14 ns
SN74V3640-7
SN74V3650-7
SN74V3660-7
SN74V3670-7
SN74V3680-7
SN74V3690-7
SN74V3640-10
SN74V3650-10
SN74V3660-10
SN74V3670-10
SN74V3680-10
SN74V3690-10
SN74V3640-15
SN74V3650-15
SN74V3660-15
SN74V3670-15
SN74V3680-15
SN74V3690-15
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
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