SN74SSTL16847
20-BIT SSTL_3 INTERFACE BUFFER
WITH 3-STATE OUTPUTS
SCBS709A – OCTOBER 1997 – REVISED MA Y 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus Family
D
Supports SSTL_3 Signal Inputs and
Outputs
D
Flow-Through Architecture Optimizes PCB
Layout
D
Meets SSTL_3 Class I and Class II
Specifications
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Packaged in Plastic Thin Shrink
Small-Outline Package
description
This 20-bit buffer is designed for 3-V to 3.6-V V
CC
operation and SSTL_3 input levels.
Data flow from A to Y is controlled by the
output-enable (OE
). When OE is high, the outputs
are in the high-impedance state.
T o ensure the high-impedance state during power
up or power down, OE
should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
The SN74SSTL16847 is characterized for
operation from 0°C to 70°C.
Copyright 1998, Texas Instruments Incorporated
Widebus is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Y1
Y2
GND
Y3
Y4
V
DDQ
Y5
Y6
GND
Y7
Y8
V
DDQ
Y9
Y10
GND
OE
V
REF
GND
Y1 1
Y12
V
DDQ
Y13
Y14
GND
Y15
Y16
V
DDQ
Y17
Y18
GND
Y19
Y20
A1
A2
GND
A3
A4
V
CC
A5
A6
GND
A7
A8
V
CC
A9
A10
GND
NC
NC
GND
A1 1
A12
V
CC
A13
A14
GND
A15
A16
V
CC
A17
A18
GND
A19
A20
NC – No internal connection
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74SSTL16847
20-BIT SSTL_3 INTERFACE BUFFER
WITH 3-STATE OUTPUTS
SCBS709A – OCTOBER 1997 – REVISED MA Y 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUT
OE A
Y
L H H
L LL
HXZ
logic diagram (positive logic)
A1
64
To 19 Other Channels
OE
16
Y1
1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
or V
DDQ
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Notes 1 and 2) –0.5 V to V
DDQ
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(VO = 0 to V
DDQ
) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
, V
DDQ
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
q
JA
(see Note 3): 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current will flow only when the output is in the high state and VO > V
DDQ
.
3. The package thermal impedance is calculated in accordance with JESD 51.
SN74SSTL16847
20-BIT SSTL_3 INTERFACE BUFFER
WITH 3-STATE OUTPUTS
SCBS709A – OCTOBER 1997 – REVISED MA Y 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN NOM MAX UNIT
V
CC
Supply voltage V
DDQ
3.6 V
V
DDQ
Output supply voltage 3 3.6 V
V
REF
Reference voltage (V
REF
= 0.45 × V
DDQ
) 1.3 1.5 1.7 V
V
TT
T ermination voltage V
REF
–50mV V
REFVREF
+50mV V
V
I
Input voltage 0 V
CC
V
V
IH
AC high-level input voltage All inputs V
REF
+400mV V
V
IL
AC low-level input voltage All inputs V
REF
–400mV V
V
IH
DC high-level input voltage All inputs V
REF
+200mV V
V
IL
DC low-level input voltage All inputs V
REF
–200mV V
I
OH
High-level output current –20
I
OL
Low-level output current 20
mA
T
A
Operating free-air temperature 0 70
_
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP†MAX UNIT
V
IK
II = –18 mA 3 V –1.2 V
IOH = –100 µA 3 V to 3.6 V VCC–0.2
V
OH
IOH = –16 mA
2.2
V
IOH = –20 mA
3 V
2.1
IOL = 100 µA 3 V to 3.6 V 0.2
V
OL
IOL = 16 mA
0.5
V
IOL = 20 mA
3 V
0.55
Data inputs, OE
VI = 2.1 V or 0.9 V, V
REF
= 1.3 V or 1.7 V
±5 µA
I
I
V
REF
V
REF
= 1.3 V or 1.7 V
3.6 V
±150 µA
I
OZ
VO = 0.9 V or 2.1 V 3.6 V ±10 µA
I
CC
VI = 2.1 V or 0.9 V, IO = 0 3.6 V 90 mA
Control inputs
2
p
C
i
A port
V
I
= 2.1 V or 0.9
V
3.3 V
2.5
pF
C
o
Y port VO = 2.1 V or 0.9 V 3.3 V 3.5 pF
†
All typical values are at VCC = 3.3 V, TA = 25°C.
SN74SSTL16847
20-BIT SSTL_3 INTERFACE BUFFER
WITH 3-STATE OUTPUTS
SCBS709A – OCTOBER 1997 – REVISED MA Y 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
Class I, V
REF
= VTT = V
DDQ
X 0.45 and CL = 10 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN MAX UNIT
t
pd
A Y 1.5 3 ns
t
en
OE
Y 1.5 4 ns
t
dis
OE
Y 1.6 4.9 ns
switching characteristics over recommended operating free-air temperature range,
Class II, V
REF
= VTT = V
DDQ
X 0.45 and CL = 30 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN MAX UNIT
t
pd
A Y 1.5 3 ns
t
en
OE
Y 1.5 4.1 ns
t
dis
OE
Y 1.5 4.8 ns
SN74SSTL16847
20-BIT SSTL_3 INTERFACE BUFFER
WITH 3-STATE OUTPUTS
SCBS709A – OCTOBER 1997 – REVISED MA Y 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
h
t
su
LOAD CIRCUIT
V
REF
†
V
IH
‡
V
IL
§
V
REF
†
V
REF
†
V
IH
‡
V
IL
§
V
IH
‡
V
IL
§
V
REF
†
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
Output
Waveform 1
(see Note B)
Output
Waveform 2
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
V
REF
†
V
REF
†
V
TT
V
IL
§
V
IL
§
V
IH
‡
V
TT
V
IH
‡
Output
Control
t
PLH
t
PHL
V
REF
†
V
REF
†
V
IH
‡
V
IL
§
V
REF
†
V
REF
†
V
OH
V
OL
Input
Output
25 Ω = SSTL_3 Class II
CL = 10 pF or 30 pF
(see Note A)
Test
Point
V
TT
V
REF
†
25 Ω
50 Ω = SSTL_3 Class I
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
V
IL
§
V
IH
‡
†
V
REF
= 0.45 V
DDQ
‡
VIH = V
REF
+400mV (AC voltage levels)
§
VIL = V
REF
–400mV (AC voltage levels)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1.25 ns/V ,
tf≤ 1.25 ns/V .
D. The outputs are measured one at a time with one transition per measurement.
E. VTT = V
REF
= V
DDQ
X 0.45
F. t
PLZ
and t
PHZ
are the same as t
dis
.
G. t
PZL
and t
PZH
are the same as ten.
H. t
PLH
and t
PHL
are the same as tpd.
Timing
Input
Data
Input
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...