Texas Instruments SN74LVTH652DBLE, SN74LVTH652DBR, SN74LVTH652DGVR, SN74LVTH652DW, SN74LVTH652DWR Datasheet

SN54LVTH652, SN74LVTH652

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS706D – AUGUST 1997 – REVISED APRIL 1999

D

State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation

D

I

and Power-Up 3-State Support Hot

off

Insertion

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With

3.3-V V

D

Support Unregulated Battery Operation

CC

)

Down to 2.7 V

D

Typical V
< 0.8 V at V

D

Latch-Up Performance Exceeds 500 mA Per

(Output Ground Bounce)

OLP

= 3.3 V, TA = 25°C

CC

JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Thin Very Small-Outline (DGV) Packages,
Ceramic Chip Carriers (FK), Ceramic Flat
(W) Package, and Ceramic (JT) DIPs

description

These bus transceivers and registers are
designed specifically for low-voltage (3.3-V) V
operation, but with the capability to provide a TTL
interface to a 5-V system environment.

CC

SN54LVTH652.. . JT OR W PACKAGE

SN74LVTH652.. . DB, DGV, DW, OR PW PACKAGE

CLKAB

OEAB

SN54LVTH652.. . FK PACKAGE

A1
A2
A3

NC

A4
A5
A6

NC – No internal connection

SAB

A1
A2
A3
A4
A5
A6
A7
A8

GND

4

5
6
7
8
9
10
11

12

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12

(TOP VIEW)

SAB

CLKAB

OEAB

321

13 14

15 16 17 18

A8

A7

GND

24

V

23

CLKBA

22

SBA

21

OEBA

20

B1

19

B2

18

B3

17

B4

16

B5

15

B6

14

B7

13

B8

CC

NC

V

28 27 26

B8B7B6

NC

CC

CLKBA

SBA

25
24
23
22
21
20
19

OEBA
B1
B2
NC
B3
B4
B5

The ’LVTH652 devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal storage registers.

Output-enable (OEAB and OEBA

) inputs are provided to control the transceiver functions. Select-control (SAB
and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for
select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between
real-time and stored data. A low input selects real-time data and a high input selects stored data. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the ’L VTH652 devices.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, T exas Instruments Incorporated

1

SN54LVTH652, SN74LVTH652

OPERATION OR FUNCTION

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS706D – AUGUST 1997 – REVISED APRIL 1999

description (continued)

Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB
and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA
when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains
at its last state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

. In this configuration, each output reinforces its input; therefore,

When V
However, to ensure the high-impedance state above 1.5 V, OE

is between 0 and 1.5 V , the device is in the high-impedance state during power up or power down.

CC

should be tied to VCC through a pullup resistor
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.

This device is fully specified for hot-insertion applications using I

and power-up 3-state. The I

off

circuitry

off

disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.

The SN54LVTH652 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH652 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OEAB OEBA CLKAB CLKBA SAB SBA A1–A8 B1–B8

L H H or L H or L X X Input Input Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ H or L X X Input Unspecified

H H ↑↑X

L X H or L ↑ X X Unspecified
L L ↑↑XX
L L X X X L Output Input Real-time B data to A bus

L L X H or L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H H or L X H X Input Output Stored A data to B bus

H L H or L H or L H H Output Output

†

The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

‡

Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.

‡

X Input Output Store A in both registers

‡

DATA I/O

‡

Output Input Store B in both registers

†

‡

Input Hold A, store B

Store A, hold B

Stored A data to B bus and

stored B data to A bus

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH652, SN74LVTH652

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS706D – AUGUST 1997 – REVISED APRIL 1999

BUS A

3 21 1 23 2 22 1 23 2 22321

OEAB

OEBA

LL

CLKABXCLKBAXSABXSBA

REAL-TIME TRANSFER

BUS B TO BUS A

BUS B

OEABOEBA

L

BUS A

HH

BUS B

CLKABXCLKBAXSABLSBA

X

REAL-TIME TRANSFER

BUS A TO BUS B

BUS A

3 21 23 2 22 3 21 1 2 22

OEAB

Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages.

OEBA

X
L
L

H
X
H

1

CLKAB CLKBAXSABXSBA

↑

XX

↑
↑↑

STORAGE FROM

A, B, OR A AND B

BUS B

X
X

X

X

Figure 1. Bus-Management Functions

BUS A

23

OEAB

OEBA

H L H or L H H

CLKAB CLKBA SAB SBA

H or L

TRANSFER STORED DA TA

TO A AND/OR B

BUS B

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3

SN54LVTH652, SN74LVTH652

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS706D – AUGUST 1997 – REVISED APRIL 1999

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages.

†

SBA

SAB

A1

A2
A3
A4
A5
A6
A7
A8

21
3
23

22

1
2

4

5
6
7
8
9
10
11

EN1 [BA]
EN2 [AB]

C4

G5

C6

G7

≥1

1

6D

1

4D

5

1

5

≥1

7
7

2

OEBA

OEAB

CLKBA

CLKAB

19
18
17
16
15
14
13

20

B1

B2
B3
B4
B5
B6
B7
B8

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

SN54LVTH652, SN74LVTH652

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS706D – AUGUST 1997 – REVISED APRIL 1999

OEBA

OEAB

CLKBA

SBA

CLKAB

SAB

A1

21

3
23

22
1

2

4

One of Eight Channels

1D

C1

C1

1D

20

B1

To Seven Other Channels

Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54LVTH652, SN74LVTH652

UNIT

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS706D – AUGUST 1997 – REVISED APRIL 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high-impedance

or power-off state, V
Voltage range applied to any output in the high state, V
Current into any output in the low state, I

Current into any output in the high state, I
Input clamp current, I

Output clamp current, I
Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

: SN54LVTH652 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .

O

SN74LVTH652 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): SN54LVTH652 48 mA. . . . . . . . . . . . . . . . . . . . . . . .

O

SN74LVTH652 64 mA. . . . . . . . . . . . . . . . . . . . . . . .

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

(see Note 3): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DGV package 139°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

recommended operating conditions (see Note 4)

SN54LVTH652 SN74LVTH652

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V

T

A

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA

Power-up ramp rate 200 200 µs/V

CC

Operating free-air temperature –55 125 –40 85 °C

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

6

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PARAMETER

TEST CONDITIONS

UNIT

V

V

V

3 V

V

V

V

V

V

V

Control inputs

CC

V

V

()

V

I

V

CC

GND

SN54LVTH652, SN74LVTH652

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS706D – AUGUST 1997 – REVISED APRIL 1999

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LVTH652 SN74LVTH652

MIN TYP†MAX MIN TYP†MAX

V

IK

OH

OL

I

I

A or B ports‡VCC = 3.6 V

I

off

I

I(hold)

I

OZPU

I

OZPD

I

CC

∆I
C

C

∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

Unused terminals at VCC or GND

§

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

¶

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

CC

i
io

A or B ports

¶

VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4

=

CC

= 2.7

CC

= 3

CC

VCC = 3.6 V, VI = VCC or GND ±1 ±1

p

VCC = 0 or 3.6 V, VI = 5.5 V 10 10

VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

= 3

CC

VCC = 3.6 V
VCC = 0 to 1.5 V, VO = 0.5 to 3 V,

OE/OE
VCC = 1.5 V to 0, VO = 0.5 to 3 V,

OE/OE

VCC = 3.6 V, IO = 0,

=

VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND

VI = 3 V or 0 4 4 pF
VO = 3 V or 0 9 9 pF

§

= don’t care

= don’t care

or

IOH = –24 mA 2
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
IOL = 32 mA 0.5 0.5
IOL = 48 mA 0.55
IOL = 64 mA 0.55

VI = 5.5 V 20 20
VI = V

CC

VI = 0 –5 –5

VI = 0.8 V 75 75
VI = 2 V –75 –75
VI = 0 to 3.6 V ±500

Outputs high 0.19 0.19
Outputs low 5 5
Outputs disabled 0.19 0.19

1 1

∗

±100

∗

±100

0.2 0.2 mA

µA

µA

±100 µA

±100 µA

mA

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

SN54LVTH652, SN74LVTH652

t

,

ns

A or B

ns

A or B

B or A

ns

SBA

SAB

‡

A or B

ns

OEBA

A

ns

OEBA

A

ns

OEAB

B

ns

OEAB

B

ns

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS706D – AUGUST 1997 – REVISED APRIL 1999

timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)

SN54LVTH652 SN74LVTH652

f

clock

t

w

su

t

h

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAX

Clock frequency 150 150 150 150 MHz
Pulse duration, CLK high or low 3.3 3.3 3.3 3.3 ns

Setup time,
A or B before CLKAB↑ or CLKBA↑

Hold time, A or B after CLKAB↑ or CLKBA↑ 1.2 1.2 0.8 0.8 ns

Data high 1.3 1.6 1.2 1.5
Data low

1.9 2.6 1.6 2.2

VCC = 2.7 V

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 2)

SN54LVTH652 SN74LVTH652

PARAMETER

f

max

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

PZH

t

PZL

t

PHZ

t

PLZ

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

These parameters are measured with the internal output state of the storage register opposite that of the bus input.

FROM

(INPUT)

CLKBA or

CLKAB

or

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN TYP†MAX MIN MAX

150 150 150 150 MHz

1.7 5 5.9 1.8 3.1 4.7 5.6

1.7 5 5.9 1.8 3.1 4.7 5.6

1.2 3.7 4.3 1.3 2.3 3.5 4.1

1.2 3.7 4.3 1.3 2.4 3.5 4.1

1.4 5.2 6.3 1.5 3.1 4.9 6

1.4 5.2 6.3 1.5 3.4 4.9 6
1 5.4 6.7 1.1 2.9 5.2 6.5
1 5.4 6.7 1.1 3.1 5.2 6.5

2.2 5.9 6.5 2.3 3.5 5.5 6.1

2.2 5.9 6.3 2.3 3.7 5.5 5.9

1.2 4.9 5.9 1.3 3 4.7 5.7

1.2 4.9 5.9 1.3 3.3 4.7 5.7

1.4 5.8 7 1.5 3.6 5.6 6.7

1.4 5.9 6.6 1.5 3.7 5.6 6.3

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 2.7 V

UNIT

UNIT

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

From Output

Under Test

CL = 50 pF

(see Note A)

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS706D – AUGUST 1997 – REVISED APRIL 1999

PARAMETER MEASUREMENT INFORMATION

6 V

500 Ω

500 Ω

S1

Open

GND

SN54LVTH652, SN74LVTH652

WITH 3-STATE OUTPUTS

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

6 V

GND

LOAD CIRCUIT

t

w

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

1.5 V

t

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

t

1.5 V

t

1.5 V1.5 V

PHL

PLH

2.7 V

0 V

V

OH

V

OL

V

OH

V

OL

2.7 V

0 V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

1.5 V

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V

t

PZL

1.5 V

t

PZH

1.5 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

t

h

1.5 V

t

VOL + 0.3 V

t

VOH – 0.3 V

PLZ

PHZ

2.7 V

0 V

2.7 V

0 V

2.7 V

0 V

3 V

V

OL

V

OH

≈ 0 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

Figure 2. Load Circuit and Voltage Waveforms

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9

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

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Copyright  1999, Texas Instruments Incorporated