Texas Instruments SN74LVTH543DBLE, SN74LVTH543DBR, SN74LVTH543DGVR, SN74LVTH543DW, SN74LVTH543DWR Datasheet

SN54LVTH543, SN74LVTH543

3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS704D – AUGUST 1997 – REVISED APRIL 1999

D

State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation

D

I

and Power-Up 3-State Support Hot

off

Insertion

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With

3.3-V V

D

Support Unregulated Battery Operation

CC

)

Down to 2.7 V

D

Typical V
< 0.8 V at V

D

Latch-Up Performance Exceeds 500 mA Per

(Output Ground Bounce)

OLP

= 3.3 V, TA = 25°C

CC

JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Thin Very Small-Outline (DGV) Packages,
Ceramic Chip Carriers (FK), Ceramic Flat
(W) Package, and Ceramic (JT) DIPs

description

SN54LVTH543...JT OR W PACKAGE

SN74LVTH543. . . DB, DGV, DW, OR PW PACKAGE

OEBA

CEAB

SN54LVTH543. . . FK PACKAGE

A2
A3
A4

NC

A5
A6
A7

(TOP VIEW)

24
23
22
21
20
19
18
17
16
15
14
13

V

CC

V

CC

CEBA
B1
B2
B3
B4
B5
B6
B7
B8
LEAB
OEAB

B1

25
24
23
22
21
20
19

B2
B3
B4
NC
B5
B6
B7

LEBA

1
2
3

A1

4

A2

5

A3

6

A4

7

A5

8

A6

9

A7

10

A8

11
12

GND

(TOP VIEW)

A1

OEBA

LEBANCCEBA

3212827

426

5
6
7
8
9
10
11

12 13

14 15 16 17 18

These octal transceivers are designed specifically
for low-voltage (3.3-V) V

operation, but with the

CC

capability to provide a TTL interface to a 5-V
system environment.

NC – No internal connection

A8

GND

CEAB

NC

LEAB

OEAB

B8

The ’LVTH543 devices contain two sets of D-type latches for temporary storage of data flowing in either
direction. Separate latch-enable (LEAB

or LEBA) and output-enable (OEAB or OEBA) inputs are provided for

each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB

LEAB

is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB
at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA

) input must be low to enter data from A or to output data from B. If CEAB is low and

and OEAB both low, the 3-state B outputs are active and reflect the data present

, LEBA, and OEBA

inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Copyright  1999, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54LVTH543, SN74LVTH543

3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS704D – AUGUST 1997 – REVISED APRIL 1999

description (continued)

When VCC is between 0 and 1.5 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE
the minimum value of the resistor is determined by the current-sinking capability of the driver.

should be tied to VCC through a pullup resistor;

This device is fully specified for hot-insertion applications using I

and power-up 3-state. The I

off

disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.

The SN54LVTH543 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH543 is characterized for operation from –40°C to 85°C.

†

, LEBA, and OEBA.

5D

1
1

4

OUTPUT

B

‡

0

22

21
20

19
18

17
16
15

B1

B2
B3

B4
B5

B6
B7
B8

logic symbol

FUNCTION TABLE

INPUTS

CEAB LEAB OEAB A

H X X X Z
X XHXZ

LHLXB
LLLLL
LLLHH

†

A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA

‡

Output level before the indicated steady-state
input conditions were established

§

A1

A2
A3
A4

A5
A6

A7
A8

2
23
1
13
11
14

3

4
5
6

7
8

9
10

1EN3
G1
1C5
2EN4
G2
2C6

3

6D

OEBA
CEBA

LEBA
OEAB
CEAB

LEAB

circuitry

off

§

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

2

OEBA

23

CEBA

1

LEBA

13

OEAB

11

CEAB

14

LEAB

SN54LVTH543, SN74LVTH543

3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS704D – AUGUST 1997 – REVISED APRIL 1999

3

A1

C1
1D

To Seven Other Channels

Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages.

C1
1D

22

B1

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high-impedance

or power-off state, V
Voltage range applied to any output in the high state, V
Current into any output in the low state, I

Current into any output in the high state, I
Input clamp current, I

Output clamp current, I
Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

: SN54LVTH543 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .

O

SN74LVTH543 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): SN54LVTH543 48 mA. . . . . . . . . . . . . . . . . . . . . . . .

O

SN74LVTH543 64 mA. . . . . . . . . . . . . . . . . . . . . . . .

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

(see Note 3): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DGV package 139°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3