Texas Instruments SN74LVTH543DBLE, SN74LVTH543DBR, SN74LVTH543DGVR, SN74LVTH543DW, SN74LVTH543DWR Datasheet
...
SN54LVTH543, SN74LVTH543
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS704D – AUGUST 1997 – REVISED APRIL 1999
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
I
and Power-Up 3-State Support Hot
off
Insertion
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
D
Support Unregulated Battery Operation
CC
)
Down to 2.7 V
D
Typical V
< 0.8 V at V
D
Latch-Up Performance Exceeds 500 mA Per
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Thin Very Small-Outline (DGV) Packages,
Ceramic Chip Carriers (FK), Ceramic Flat
(W) Package, and Ceramic (JT) DIPs
description
SN54LVTH543...JT OR W PACKAGE
SN74LVTH543. . . DB, DGV, DW, OR PW PACKAGE
OEBA
CEAB
SN54LVTH543. . . FK PACKAGE
A2
A3
A4
NC
A5
A6
A7
(TOP VIEW)
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
V
CC
CEBA
B1
B2
B3
B4
B5
B6
B7
B8
LEAB
OEAB
B1
25
24
23
22
21
20
19
B2
B3
B4
NC
B5
B6
B7
LEBA
1
2
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10
A8
11
12
GND
(TOP VIEW)
A1
OEBA
LEBANCCEBA
3212827
426
5
6
7
8
9
10
11
12 13
14 15 16 17 18
These octal transceivers are designed specifically
for low-voltage (3.3-V) V
operation, but with the
CC
capability to provide a TTL interface to a 5-V
system environment.
NC – No internal connection
A8
GND
CEAB
NC
LEAB
OEAB
B8
The ’LVTH543 devices contain two sets of D-type latches for temporary storage of data flowing in either
direction. Separate latch-enable (LEAB
or LEBA) and output-enable (OEAB or OEBA) inputs are provided for
each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB
LEAB
is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB
at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA
) input must be low to enter data from A or to output data from B. If CEAB is low and
and OEAB both low, the 3-state B outputs are active and reflect the data present
, LEBA, and OEBA
inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LVTH543, SN74LVTH543
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS704D – AUGUST 1997 – REVISED APRIL 1999
description (continued)
When VCC is between 0 and 1.5 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE
the minimum value of the resistor is determined by the current-sinking capability of the driver.
should be tied to VCC through a pullup resistor;
This device is fully specified for hot-insertion applications using I
and power-up 3-state. The I
off
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH543 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH543 is characterized for operation from –40°C to 85°C.
†
, LEBA, and OEBA.
5D
1
1
4
OUTPUT
B
‡
0
22
21
20
19
18
17
16
15
B1
B2
B3
B4
B5
B6
B7
B8
logic symbol
FUNCTION TABLE
INPUTS
CEAB LEAB OEAB A
H X X X Z
X XHXZ
LHLXB
LLLLL
LLLHH
†
A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA
‡
Output level before the indicated steady-state
input conditions were established
§
A1
A2
A3
A4
A5
A6
A7
A8
2
23
1
13
11
14
3
4
5
6
7
8
9
10
1EN3
G1
1C5
2EN4
G2
2C6
3
6D
OEBA
CEBA
LEBA
OEAB
CEAB
LEAB
circuitry
off
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
2
OEBA
23
CEBA
1
LEBA
13
OEAB
11
CEAB
14
LEAB
SN54LVTH543, SN74LVTH543
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS704D – AUGUST 1997 – REVISED APRIL 1999
3
A1
C1
1D
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages.
C1
1D
22
B1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high-impedance
or power-off state, V
Voltage range applied to any output in the high state, V
Current into any output in the low state, I
Current into any output in the high state, I
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
: SN54LVTH543 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .
O
SN74LVTH543 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): SN54LVTH543 48 mA. . . . . . . . . . . . . . . . . . . . . . . .
O
SN74LVTH543 64 mA. . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(see Note 3): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 139°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LVTH543, SN74LVTH543
UNIT
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS704D – AUGUST 1997 – REVISED APRIL 1999
recommended operating conditions (see Note 4)
SN54LVTH543 SN74LVTH543
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
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PARAMETER
TEST CONDITIONS
UNIT
V
V
V
3 V
V
V
V
V
V
V
Control inputs
CC
V
V
()
V
I
V
CC
GND
SN54LVTH543, SN74LVTH543
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS704D – AUGUST 1997 – REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH543 SN74LVTH543
MIN TYP†MAX MIN TYP†MAX
V
IK
OH
OL
I
I
A or B ports‡VCC = 3.6 V
I
off
I
I(hold)
I
OZPU
I
OZPD
I
CC
∆I
CC
C
i
C
io
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
Unused terminals are at VCC or GND.
§
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
A or B ports
¶
VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4
=
CC
= 2.7
CC
= 3
CC
VCC = 3.6 V, VI = VCC or GND ±1 ±1
p
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
= 3
CC
VCC = 3.6 V
VCC = 0 to 1.5 V, VO = 0.5 to 3 V,
OE
= don’t care
VCC = 1.5 V to 0, VO = 0.5 to 3 V,
OE
= don’t care
VCC = 3.6 V, IO = 0,
=
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = 3 V or 0 4 4 pF
VO = 3 V or 0 9 9 pF
§
or
IOH = –24 mA 2
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
IOL = 32 mA 0.5 0.5
IOL = 48 mA 0.55
IOL = 64 mA 0.55
VI = 5.5 V 20 20
VI = V
CC
VI = 0 –5 –5
VI = 0.8 V 75 75
VI = 2 V –75 –75
VI = 0 to 3.6 V ±500
Outputs high 0.19 0.19
Outputs low 5 5
Outputs disabled 0.19 0.19
1 1
∗
±100
∗
±100
0.2 0.2 mA
µA
µA
±100 µA
±100 µA
mA
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LVTH543, SN74LVTH543
A or B before
tsuSetup time
ns
A or B before
A or B after
thHold time
ns
A or B
B or A
ns
LE
A or B
ns
OE
A or B
ns
OE
A or B
ns
CE
A or B
ns
CE
A or B
ns
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS704D – AUGUST 1997 – REVISED APRIL 1999
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH543 SN74LVTH543
VCC = 3.3 V
± 0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
t
w
Pulse duration, LEAB or LEBA low 3.3 3.3 3.3 3.3 ns
A or B before
p
LEAB or LEBA↑
A or B before
CEAB or CEBA↑
A or B after
LEAB or LEBA↑
A or B after
CEAB or CEBA↑
Data high 0.4 0.4 0.4 0.4
Data low 1 1.5 1 1.5
Data high 0.2 0.2 0.2 0.2
Data low 0.7 1.2 0.7 1.2
Data high 1.5 0.6 1.5 0.6
Data low 1.3 1.5 1.3 1.5
Data high 1.6 0.5 1.6 0.5
Data low 1.4 1.6 1.4 1.6
VCC = 2.7 V
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVTH543 SN74LVTH543
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
†
All typical values are at VCC = 3.3 V, TA = 25°C.
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
1.2 3.9 4.5 1.3 2.5 3.7 4.3
1.2 3.9 4.5 1.3 2.5 3.7 4.3
1.2 5.1 6.1 1.3 2.9 4.7 5.9
1.2 5.1 6.1 1.3 2.9 4.7 5.9
1 5.1 6.4 1.1 2.9 4.9 6.2
1 5.1 6.4 1.1 3.2 4.9 6.2
1.9 5.6 6.2 2 3.4 5.3 5.9
1.9 5.6 6.2 2 3.7 5.3 5.9
1.2 5.5 7 1.3 3.2 5.3 6.8
1.2 5.5 7 1.3 3.5 5.3 6.8
2.2 5.7 6.2 2.3 3.8 5.4 5.9
2.2 5.7 5.9 2.3 3.9 5.4 5.6
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
VCC = 2.7 V
UNIT
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
SCBS704D – AUGUST 1997 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
6 V
500 Ω
500 Ω
S1
Open
GND
SN54LVTH543, SN74LVTH543
WITH 3-STATE OUTPUTS
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
LOAD CIRCUIT
t
w
Input
Input
t
Output
t
Output
INVERTING AND NONINVERTING OUTPUTS
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
PLH
1.5 V
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
1.5 V
t
1.5 V1.5 V
PHL
PLH
2.7 V
0 V
V
OH
V
OL
V
OH
V
OL
2.7 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
h
1.5 V
t
VOL + 0.3 V
t
VOH – 0.3 V
PLZ
PHZ
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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7
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1999, Texas Instruments Incorporated
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