Texas Instruments SN74LVTH541DWR, SN74LVTH541PWLE, SN74LVTH541PWR, SN74LVTH541DBLE, SN74LVTH541DBR Datasheet

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SN54LVTH541, SN74LVTH541
3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS682E – MARCH 1997 – REVISED APRIL 1999
D
D
I
and Power-Up 3-State Support Hot
off
Insertion
D
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
D
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V
D
Support Unregulated Battery Operation Down to 2.7 V
D
Typical V < 0.8 V at V
D
Latch-Up Performance Exceeds 500 mA Per
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
JESD 17
D
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Ceramic (J) DIPs
description
CC
SN54LVTH541...J OR W PACKAGE
SN74LVTH541. . . DB, DW, OR PW PACKAGE
)
SN54LVTH541. . . FK PACKAGE
A3 A4 A5 A6 A7
(TOP VIEW)
OE1
1
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
GND
10
(TOP VIEW)
A2A1OE1
3212019
4 5 6 7 8
910111213
A8
GND
Y8
20 19 18 17 16 15 14 13 12 11
V
CC
Y7
V
CC
OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
18 17 16 15 14
Y6 OE2
Y1 Y2 Y3 Y4 Y5
These octal buffers/drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The ’L VTH541 devices are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 input is high, all outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When V
However, to ensure the high-impedance state above 1.5 V, OE
is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.
CC
should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using I
and power-up 3-state. The I
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
or OE2)
circuitry
off
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1
SN54LVTH541, SN74LVTH541
3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS682E – MARCH 1997 – REVISED APRIL 1999
description (continued)
The SN54LVTH541 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVTH541 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE INPUTS
OE1 OE2 A
L L L L
L LH H HXX Z XHX Z
OUTPUT
Y
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
OE1
OE2
A1 A2 A3 A4 A5 A6 A7 A8
1
19
2 3 4 5 6 7 8 9
&
EN
1
logic diagram (positive logic)
1
OE1
19
OE2
18 17 16 15 14 13 12 11
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
218
A1
To Seven Other Channels
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Y1
UNIT
SN54LVTH541, SN74LVTH541
3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS682E – MARCH 1997 – REVISED APRIL 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V Input voltage range, V
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Voltage range applied to any output in the high-impedance
or power-off state, V Voltage range applied to any output in the high state, V Current into any output in the low state, I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
: SN54LVTH541 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .
O
SN74LVTH541 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
(see Note 2): SN54LVTH541 48 mA. . . . . . . . . . . . . . . . . . . . . . .
O
SN74LVTH541 64 mA. . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I Output clamp current, I Package thermal impedance, θ
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
SN54LVTH541 SN74LVTH541
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
t/v Input transition rise or fall rate 10 10 ns/Vt/V
T
A
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2.7 3.6 2.7 3.6 V High-level input voltage 2 2 V Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.5 V High-level output current –24 –32 mA Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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