How it Works
Datasheet
Loading...
SN74LVTH374PWLE

Datasheet SN74LVTH374DBLE, SN74LVTH374DBR, SN74LVTH374DW, SN74LVTH374DWR, SN74LVTH374PWLE Datasheet (Texas Instruments)

...
Download
SN54LVTH374, SN74LVTH374
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS683E – MARCH 1997 – REVISED APRIL 1999
D
D
I
and Power-Up 3-State Support Hot
off
Insertion
D
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
D
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V
D
Support Unregulated Battery Operation Down to 2.7 V
D
Typical V < 0.8 V at V
D
Latch-Up Performance Exceeds 500 mA Per
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
JESD 17
D
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Ceramic (J) DIPs
description
CC
SN54LVTH374...J OR W PACKAGE
SN74LVTH374. . . DB, DW, OR PW PACKAGE
)
SN54LVTH374. . . FK PACKAGE
2D 2Q 3Q 3D 4D
(TOP VIEW)
OE
1Q 1D 2D 2Q 3Q 3D 4D 4Q
GND
(TOP VIEW)
3 2 1 20 19
4 5 6 7 8
9 10 11 12 13
1 2 3 4 5 6 7 8 9 10
1D1QOE
4Q
CLK
GND
20 19 18 17 16 15 14 13 12 11
V
CC
5Q
V
CC
8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK
8Q
18 17 16 15 14
5D
8D 7D 7Q 6Q 6D
These octal flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The eight flip-flops of the ’LVTH374 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE
) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE
does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state. When V
However, to ensure the high-impedance state above 1.5 V, OE
is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.
CC
should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LVTH374, SN74LVTH374
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS683E – MARCH 1997 – REVISED APRIL 1999
description (continued)
These devices are fully specified for hot-insertion applications using I
and power-up 3-state. The I
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
The SN54LVTH374 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVTH374 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
logic symbol
INPUTS
OE CLK D
L ↑ H H L ↑ LL LH or L X Q
H X X Z
†
OE
CLK
1D 2D 3D
4D 5D 6D 7D 8D
1 11
3 4 7
8 13 14 17 18
EN
C1
1D
OUTPUT
Q
0
12 15 16 19
2
1Q
5
2Q
6
3Q
9
4Q 5Q 6Q 7Q 8Q
circuitry
off
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
OE
11
CLK
3
1D
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C1
1D
2
1Q
UNIT
SN54LVTH374, SN74LVTH374
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS683E – MARCH 1997 – REVISED APRIL 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V Input voltage range, V
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
†
Voltage range applied to any output in the high-impedance
or power-off state, V Voltage range applied to any output in the high state, V Current into any output in the low state, I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
: SN54LVTH374 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .
O
SN74LVTH374 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
(see Note 2): SN54LVTH374 48 mA. . . . . . . . . . . . . . . . . . . . . . .
O
SN74LVTH374 64 mA. . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I Output clamp current, I Package thermal impedance, θ
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
SN54LVTH374 SN74LVTH374
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 10 10 ns/V ∆t/∆V
T
A
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2.7 3.6 2.7 3.6 V High-level input voltage 2 2 V Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.5 V High-level output current –24 –32 mA Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LVTH374, SN74LVTH374
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
V
V
V
V
V
V
I
A
D
V
3.6 V
V
V
I
I(hold)
Data in uts
µA
V
CC
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS683E – MARCH 1997 – REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LVTH374 SN74LVTH374
MIN TYP†MAX MIN TYP†MAX
V
IK
OH
OL
I
I
off
I
OZH
I
OZL
I
OZPU
I
OZPD
I
CC
∆I
CC
C
i
C
o
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. †
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Control inputs VCC = 3.6 V, VI = VCC or GND ±1 ±1
ata inputs
p
§
VCC = 2.7 V, II = –18 mA –1.2 –1.2 V VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2 VCC = 2.7 V, IOH = –8 mA 2.4 2.4
= 3
CC
= 2.7
CC
= 3
CC
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
=
CC
VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
= 3
CC
VCC = 3.6 V‡, VI = 0 to 3.6 V VCC = 3.6 V, VO = 3 V 5 5 µA
VCC = 3.6 V, VO = 0.5 V –5 –5 µA VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE
= don’t care
VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE
= don’t care
=
= 3.6 V, IO = 0, VI = VCC or GND
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND
VI = 3 V or 0 3 3 pF VO = 3 V or 0 7 7 pF
IOH = –24 mA 2 IOH = –32 mA 2 IOL = 100 µA 0.2 0.2 IOL = 24 mA 0.5 0.5 IOL = 16 mA 0.4 0.4 IOL = 32 mA 0.5 0.5 IOL = 48 mA 0.55 IOL = 64 mA 0.55
VI = V
CC
VI = 0 –5 –5
VI = 0.8 V 75 75 VI = 2 V –75 –75
Outputs high 0.19 0.19 Outputs low 5 5 Outputs disabled 0.19 0.19
1 1
500
–750
∗
±100
∗
±100
0.2 0.2 mA
±100 µA
±100 µA
µ
mA
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLK
Q
ns
OE
Q
ns
OE
Q
ns
SN54LVTH374, SN74LVTH374
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS683E – MARCH 1997 – REVISED APRIL 1999
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVTH374 SN74LVTH374
f
clock
t
w
t
su
t
h
VCC = 3.3 V
± 0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
Clock frequency 150 150 150 150 MHz Pulse duration, CLK high or low 3.3 3.3 3.3 3.3 ns Setup time, data before CLK↑ 1.6 2 1.5 2 ns Hold time, data after CLK↑ 0.8 0.5 0.8 0 ns
VCC = 2.7 V
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
†
All typical values are at VCC = 3.3 V, TA = 25°C.
= 50 pF (unless otherwise noted) (see Figure 1)
L
SN54LVTH374 SN74LVTH374
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
150 150 150 150 MHz
1.7 4.7 5.3 1.8 2.9 4.5 5
1.7 4.5 4.6 1.8 2.9 4.2 4.3
1.2 4.9 5.7 1.3 2.8 4.7 5.6
1.5 4.8 5.4 1.6 3 4.7 5.2
1.8 4.8 5 1.9 3 4.6 4.9
1.9 4.9 5 2 3.1 4.5 4.6
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
VCC = 2.7 V
UNIT
UNIT
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LVTH374, SN74LVTH374
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS683E – MARCH 1997 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
6 V
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
500 Ω
S1
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
LOAD CIRCUIT
t
w
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
1.5 V 1.5 V
t
PHL
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
t
PHL
t
PLH
2.7 V
0 V
V
OH
V
OL
V
OH
V
OL
2.7 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
h
1.5 V
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Loading...
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use