Texas Instruments SN74LVTH373PWLE, SN74LVTH373PWR, SN74LVTH373DBLE, SN74LVTH373DBR, SN74LVTH373DW Datasheet
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SN54LVTH373, SN74LVTH373
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS689E – MAY 1997 – REVISED APRIL 1999
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
I
and Power-Up 3-State Support Hot
off
Insertion
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
D
Support Unregulated Battery Operation
CC
)
Down to 2.7 V
D
Typical V
< 0.8 V at V
D
Latch-Up Performance Exceeds 500 mA Per
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Ceramic (J)
DIPs
SN54LVTH373...J OR W PACKAGE
SN74LVTH373. . . DB, DW, OR PW PACKAGE
SN54LVTH373. . . FK PACKAGE
2D
2Q
3Q
3D
4D
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
3 2 1 20 19
4
5
6
7
8
9 10 11 12 13
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
(TOP VIEW)
1D1QOE
4Q
V
LE
GND
CC
5Q
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
8Q
18
17
16
15
14
5D
CC
8D
7D
7Q
6Q
6D
description
These octal latches are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to
provide a TTL interface to a 5-V system environment.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
When V
is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
) input can be used to place the eight outputs in either a normal logic state (high
should be tied to VCC through a pullup resistor;
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LVTH373, SN74LVTH373
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS689E – MAY 1997 – REVISED APRIL 1999
description (continued)
These devices are fully specified for hot-insertion applications using I
and power-up 3-state. The I
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH373 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH373 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each latch)
logic symbol
INPUTS
OE LE D
L H H H
L HL L
LLX Q
HXX Z
†
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
1
11
3
4
7
8
13
14
17
18
EN
C1
1D
OUTPUT
Q
0
12
15
16
19
2
1Q
5
2Q
6
3Q
9
4Q
5Q
6Q
7Q
8Q
circuitry
off
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
OE
11
LE
3
1D
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C1
1D
2
1Q
UNIT
SN54LVTH373, SN74LVTH373
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS689E – MAY 1997 – REVISED APRIL 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
†
Voltage range applied to any output in the high-impedance
or power-off state, V
Voltage range applied to any output in the high state, V
Current into any output in the low state, I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
: SN54LVTH373 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 1) –0.5 V to V
O
CC
+ 0.5 V. . . . . . . . . . . . .
SN74LVTH373 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
(see Note 2): SN54LVTH373 48 mA. . . . . . . . . . . . . . . . . . . . . . .
O
SN74LVTH373 64 mA. . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
SN54LVTH373 SN74LVTH373
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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