Datasheet SN74LVTH2952DBLE, SN74LVTH2952DBR, SN74LVTH2952DGVR, SN74LVTH2952DW, SN74LVTH2952DWR Datasheet (Texas Instruments)

SN54LVTH2952, SN74LVTH2952

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS710D – OCTOBER 1997 – REVISED APRIL 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation

D

I

off

and Power-Up 3-State Support Hot

Insertion

D

Bus-Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With

3.3-V V

CC

)

D

Support Unregulated Battery Operation
Down to 2.7 V

D

T ypical V

OLP

(Output Ground Bounce)

< 0.8 V at V

CC

= 3.3 V, TA = 25°C

D

Latch-Up Performance Exceeds 500 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Thin Very Small-Outline (DGV) Packages,
Ceramic Chip Carriers (FK), and Ceramic
(JT) DIPs

description

These octal bus transceivers and registers are
designed specifically for low-voltage (3.3-V) V

CC

operation, but with the capability to provide a TTL
interface to a 5-V system environment.

The ’LVTH2952 devices consist of two 8-bit back-to-back registers that store data flowing in both directions
between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition
of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB

or CLKENBA) input is low.

Taking the output-enable (OEAB

or OEBA) input low accesses the data on either port.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V

CC

is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, OE

should be tied to VCC through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.

Copyright  1999, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

B8
B7
B6
B5
B4
B3
B2
B1

OEAB

CLKAB

CLKENAB

GND

V

CC

A8
A7
A6
A5
A4
A3
A2
A1
OEBA
CLKBA
CLKENBA

SN54LVTH2952...JT PACKAGE

SN74LVTH2952. . . DB, DGV, DW, OR PW PACKAGE

(TOP VIEW)

CLKAB

CLKENAB

GND

NC

CLKENBA

CLKBA

OEBA

B6

NC

A7

V

B7

B8

A8

CC

3212827

12 13 14 15 16 17 18

5
6
7
8
9
10
11

25
24
23
22
21
20
19

A6
A5
A4
NC
A3
A2
A1

B5
B4
B3

NC

B2
B1

OEAB

426

SN54LVTH2952. . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LVTH2952, SN74LVTH2952

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS710D – OCTOBER 1997 – REVISED APRIL 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

These devices are fully specified for hot-insertion applications using I

off

and power-up 3-state. The I

off

circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.

The SN54L VTH2952 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH2952 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

†

INPUTS

OUTPUT

CLKENAB CLKAB OEAB A

B

H X L X B

0

‡

X H or L L X B

0

‡

L ↑ LL L
L ↑ LH H
X X HX Z

†

A-to-B data flow is shown; B-to-A data flow is similar
but uses CLKENBA

, CLKBA, and OEBA.

‡

Level of B before the indicated steady-state input
conditions were established

logic symbol

§

B1

8

5D

A1

16

A2

17

A3

18

A4

19

EN3

15

1 C5

B2

7

B3

6

B4

5

A5

20

A6

21

A7

22

A8

23

B5

4

B6

3

B7

2

B8

1

G2

11

G1

13

EN4

9

2 C6

OEBA

CLKENBA

OEAB

CLKENAB

14

CLKBA

10

CLKAB

§

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DGV , DW, JT, and PW packages.

4

1
16D

3

SN54LVTH2952, SN74LVTH2952

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS710D – OCTOBER 1997 – REVISED APRIL 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

C1

C1

1D

1D

To Seven Other Channels

B1

A1

OEBA

CLKBA

CLKENBA

OEAB

CLKAB

CLKENAB

Pin numbers shown are for the DB, DGV , DW, JT, and PW packages.

11

10

9

13

14

15

16

8

SN54LVTH2952, SN74LVTH2952

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS710D – OCTOBER 1997 – REVISED APRIL 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high-impedance

or power-off state, V

O

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state, V

O

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .

Current into any output in the low state, I

O

: SN54LVTH2952 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74LVTH2952 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the high state, I

O

(see Note 2): SN54LVTH2952 48 mA. . . . . . . . . . . . . . . . . . . . . .

SN74LVTH2952 64 mA. . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(V

O

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 3): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 139°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

SN54LVTH2952 SN74LVTH2952

MIN MAX MIN MAX

UNIT

V

CC

Supply voltage 2.7 3.6 2.7 3.6 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.8 0.8 V

V

I

Input voltage 5.5 5.5 V

I

OH

High-level output current –24 –32 mA

I

OL

Low-level output current 48 64 mA

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V

CC

Power-up ramp rate 200 200 µs/V

T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

SN54LVTH2952, SN74LVTH2952

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS710D – OCTOBER 1997 – REVISED APRIL 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LVTH2952 SN74LVTH2952

PARAMETER

TEST CONDITIONS

MIN TYP†MAX MIN TYP†MAX

UNIT

V

IK

VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4

V

OH

IOH = –24 mA 2

V

V

CC

=

3 V

IOH = –32 mA 2
IOL = 100 µA 0.2 0.2

V

CC

= 2.7

V

IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4

V

OL

IOL = 32 mA 0.5 0.5

V

V

CC

= 3

V

IOL = 48 mA 0.55
IOL = 64 mA 0.55

p

VCC = 3.6 V, VI = VCC or GND ±1 ±1

Control inputs

VCC = 0 or 3.6 V, VI = 5.5 V 10 10

I

I

VI = 5.5 V 20 20

µA

A or B ports‡VCC = 3.6 V

VI = V

CC

1 1

VI = 0 –5 –5

I

off

VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

VI = 0.8 V 75 75

I

I(hold)

A or B ports

V

CC

= 3

V

VI = 2 V –75 –75

µA

()

VCC = 3.6 V§, VI = 0 to 3.6 V ±500

I

OZPU

VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,

OE

= don’t care

±100

∗

±100 µA

I

OZPD

VCC = 1.5 V to 0, VO = 0.5 V to 3 V,

OE

= don’t care

±100

∗

±100 µA

=

Outputs high 0.19 0.19

I

CC

V

CC

= 3.6 V,

IO = 0,

Outputs low 5 5

mA

VI = VCC or GND

Outputs disabled 0.19 0.19

∆I

CC

¶

VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,

Other inputs at VCC or GND

0.2 0.2 mA

C

i

VI = 3 V or 0 4 4 pF

C

io

VO = 3 V or 0 9 9 pF

∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

Unused terminals at VCC or GND

§

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

¶

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

SN54LVTH2952, SN74LVTH2952

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS710D – OCTOBER 1997 – REVISED APRIL 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirement over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)

SN54LVTH2952 SN74LVTH2952

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN MAX MIN MAX MIN MAX MIN MAX

f

clock

Clock frequency 150 150 150 150 MHz

CLK high 3.3 3.3 3.3 3.3

twPulse duration

CLK low 3.3 3.3 3.3 3.3

ns

Data high 1.6 2.2 1.5 2.1

A

or B before

CLK↑

Data low 1.6 2.2 1.5 2.1

t

su

Set

up time

Data high 1.6 1.9 1.5 1.8

ns

CE bef

ore

CLK↑

Data low 2 2.6 1.9 2.5

A or B after CLK↑

1 0.2 1 0.2

t

h

Hold time

CE after CLK↑

1.2 0.2 1.2 0.2

ns

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

SN54LVTH2952 SN74LVTH2952

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN MAX MIN MAX MIN TYP†MAX MIN MAX

f

max

150 150 150 150 MHz

t

PLH

CLKBA or

1.2 4.8 5.5 1.3 2.9 4.6 5.3

t

PHL

CLKAB

A or B

1.2 4.8 5.5 1.3 3.1 4.6 5.3

ns

t

PZH

1 4.8 5.9 1.1 2.6 4.6 5.8

t

PZL

OEBA

or

OEAB

A or B

1 4.8 5.9 1.1 3 4.6 5.8

ns

t

PHZ

1.2 5.6 6 1.3 3.6 5.4 5.9

t

PLZ

OEBA or OEAB

A or B

1.5 5.4 5.6 1.6 3.6 5.1 5.3

ns

†

All typical values are at TA = 25°C.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

SN54LVTH2952, SN74LVTH2952

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS710D – OCTOBER 1997 – REVISED APRIL 1999

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

t

h

t

su

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

S1

6 V

Open

GND

500 Ω

500 Ω

Data Input

Timing Input

1.5 V

2.7 V

0 V

1.5 V 1.5 V

2.7 V

0 V

2.7 V

0 V

1.5 V 1.5 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

1.5 V 1.5 V

2.7 V

0 V

1.5 V1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

1.5 V

1.5 V

3 V

0 V

1.5 V
VOL + 0.3 V

1.5 V

VOH – 0.3 V

≈ 0 V

2.7 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

6 V

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

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any product or service without notice, and advise customers to obtain the latest version of relevant information
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright  1999, Texas Instruments Incorporated