Texas Instruments SN74LVTH2952DBLE, SN74LVTH2952DBR, SN74LVTH2952DGVR, SN74LVTH2952DW, SN74LVTH2952DWR Datasheet

SN54LVTH2952, SN74LVTH2952

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS710D – OCTOBER 1997 – REVISED APRIL 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation

D

I

off

and Power-Up 3-State Support Hot

Insertion

D

Bus-Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With

3.3-V V

CC

)

D

Support Unregulated Battery Operation
Down to 2.7 V

D

T ypical V

OLP

(Output Ground Bounce)

< 0.8 V at V

CC

= 3.3 V, TA = 25°C

D

Latch-Up Performance Exceeds 500 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Thin Very Small-Outline (DGV) Packages,
Ceramic Chip Carriers (FK), and Ceramic
(JT) DIPs

description

These octal bus transceivers and registers are
designed specifically for low-voltage (3.3-V) V

CC

operation, but with the capability to provide a TTL
interface to a 5-V system environment.

The ’LVTH2952 devices consist of two 8-bit back-to-back registers that store data flowing in both directions
between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition
of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB

or CLKENBA) input is low.

Taking the output-enable (OEAB

or OEBA) input low accesses the data on either port.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V

CC

is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, OE

should be tied to VCC through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.

Copyright  1999, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

B8
B7
B6
B5
B4
B3
B2
B1

OEAB

CLKAB

CLKENAB

GND

V

CC

A8
A7
A6
A5
A4
A3
A2
A1
OEBA
CLKBA
CLKENBA

SN54LVTH2952...JT PACKAGE

SN74LVTH2952. . . DB, DGV, DW, OR PW PACKAGE

(TOP VIEW)

CLKAB

CLKENAB

GND

NC

CLKENBA

CLKBA

OEBA

B6

NC

A7

V

B7

B8

A8

CC

3212827

12 13 14 15 16 17 18

5
6
7
8
9
10
11

25
24
23
22
21
20
19

A6
A5
A4
NC
A3
A2
A1

B5
B4
B3

NC

B2
B1

OEAB

426

SN54LVTH2952. . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LVTH2952, SN74LVTH2952

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS710D – OCTOBER 1997 – REVISED APRIL 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

These devices are fully specified for hot-insertion applications using I

off

and power-up 3-state. The I

off

circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.

The SN54L VTH2952 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH2952 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

†

INPUTS

OUTPUT

CLKENAB CLKAB OEAB A

B

H X L X B

0

‡

X H or L L X B

0

‡

L ↑ LL L
L ↑ LH H
X X HX Z

†

A-to-B data flow is shown; B-to-A data flow is similar
but uses CLKENBA

, CLKBA, and OEBA.

‡

Level of B before the indicated steady-state input
conditions were established

logic symbol

§

B1

8

5D

A1

16

A2

17

A3

18

A4

19

EN3

15

1 C5

B2

7

B3

6

B4

5

A5

20

A6

21

A7

22

A8

23

B5

4

B6

3

B7

2

B8

1

G2

11

G1

13

EN4

9

2 C6

OEBA

CLKENBA

OEAB

CLKENAB

14

CLKBA

10

CLKAB

§

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DGV , DW, JT, and PW packages.

4

1
16D

3

SN54LVTH2952, SN74LVTH2952

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS710D – OCTOBER 1997 – REVISED APRIL 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

C1

C1

1D

1D

To Seven Other Channels

B1

A1

OEBA

CLKBA

CLKENBA

OEAB

CLKAB

CLKENAB

Pin numbers shown are for the DB, DGV , DW, JT, and PW packages.

11

10

9

13

14

15

16

8