Texas Instruments SN74LVTH273PWR, SN74LVTH273DBLE, SN74LVTH273DBR, SN74LVTH273DW, SN74LVTH273DWR Datasheet
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SN54LVTH273, SN74LVTH273
3.3-V ABT OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCBS136K – MAY 1992 – REVISED APRIL 1999
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
D
Support Unregulated Battery Operation
CC
)
Down to 2.7 V
D
Buffered Clock and Direct-Clear Inputs
D
Individual Data Input to Each Flip-Flop
D
Typical V
< 0.8 V at V
D
I
off
Supports Partial-Power-Down-Mode
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
Operation
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) DIPs
SN54LVTH273...J PACKAGE
SN74LVTH273.. . DB, DW, OR PW PACKAGE
SN54LVTH273. . . FK PACKAGE
2D
2Q
3Q
3D
4D
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
4
5
6
7
8
9 10 11 12 13
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
(TOP VIEW)
GND
V
CLK
CC
5Q
1D1QCLR
3 2 1 20 19
4Q
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
8Q
18
17
16
15
14
5D
8D
7D
7Q
6Q
6D
description
These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
The ’L VTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D)
inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the
clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time
of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has
no effect at the output.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
These devices are fully specified for partial-power-down applications using I
outputs, preventing damaging current backflow through the devices when they are powered down.
The SN54LVTH273 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH273 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
. The I
off
Copyright 1999, Texas Instruments Incorporated
circuitry disables the
off
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LVTH273, SN74LVTH273
OUTPUT
3.3-V ABT OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCBS136K – MAY 1992 – REVISED APRIL 1999
CLR
L X X L
H ↑ HH
H↑LL
HH or L X Q
FUNCTION TABLE
(each flip-flop)
INPUTS
CLK D
OUTPUT
Q
0
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
CLR
CLK
1D
2D
3D
4D
5D
6D
7D
8D
1
11
3
4
7
8
13
14
17
18
R
C1
1D
logic diagram (positive logic)
CLK
1D
3 4 7 8 13 14 17 18
11
CLK(I)
1D
C1
R
2D
1D
C1
R
3D
1D
R
C1
4D
5D
1D
C1
R
1D
R
C1
12
15
16
19
2
1Q
5
2Q
6
3Q
9
4Q
5Q
6Q
7Q
8Q
6D
1D
C1
R
7D
1D
R
C1
8D
1D
C1
R
CLR
2
1
R
2 5 6 9 12 15 16 19
1Q
2Q
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3Q
4Q
5Q
6Q
7Q
8Q
UNIT
SN54LVTH273, SN74LVTH273
3.3-V ABT OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCBS136K – MAY 1992 – REVISED APRIL 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the power-off state, V
Voltage range applied to any output in the high state, V
Current into any output in the low state, I
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
O
: SN54LVTH273 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . .
O
(see Note 1) –0.5 V to V
CC
†
+ 0.5 V. . . . . . . . . . . . .
SN74LVTH273 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
(see Note 2): SN54LVTH273 48 mA. . . . . . . . . . . . . . . . . . . . . . .
O
SN74LVTH273 64 mA. . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
SN54LVTH273 SN74LVTH273
MIN MAX MIN MAX
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 10 10 ns/V
T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2.7 3.6 2.7 3.6 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 5.5 5.5 V
I
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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