Datasheet SN74LVTH245ADBLE, SN74LVTH245ADBR, SN74LVTH245ADW, SN74LVTH245ADWR, SN74LVTH245APWLE Datasheet (Texas Instruments)

SN54LVTH245A, SN74LVTH245A

3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS130P – MAY 1992 – REVISED APRIL 1999

D

State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation

D

Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V

D

Support Unregulated Battery Operation
Down to 2.7 V

D

Typical V
< 0.8 V at V

D

I

off

and Power-Up 3-State Support Hot

(Output Ground Bounce)

OLP

= 3.3 V, TA = 25°C

CC

Insertion

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Latch-Up Performance Exceeds 500 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Packages, and Ceramic
(J) DIPs

description

CC

SN54LVTH245A...J OR W PACKAGE

SN74LVTH245A. . . DB, DW, OR PW PACKAGE

)

SN54LVTH245A. . . FK PACKAGE

A3
A4
A5
A6
A7

(TOP VIEW)

1

DIR

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

GND

10

(TOP VIEW)

A2A1DIR

3212019

4
5
6
7
8

10 11 12 13

9

A8

GND

B8

20
19
18
17
16
15
14
13
12
11

V

CC

B7

V
OE
B1
B2
B3
B4
B5
B6
B7
B8

18
17
16
15
14

B6 OE

CC

B1
B2
B3
B4
B5

These octal bus transceivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.

These devices are designed for asynchronous communication between data buses. They transmit data from
the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE

) input can be used to disable the devices so the buses are effectively isolated.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V

However, to ensure the high-impedance state above 1.5 V, OE

is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.

CC

should be tied to VCC through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I

and power-up 3-state. The I

off

disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.

The SN54L VTH245A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH245A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1999, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

circuitry

off

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54LVTH245A, SN74LVTH245A

OPERATION

3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS130P – MAY 1992 – REVISED APRIL 1999

INPUTS

OE DIR

L L B data to A bus
L H A data to B bus

H X Isolation

FUNCTION TABLE

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

OE

DIR

A1

A2
A3
A4
A5
A6
A7
A8

19
1

2

3
4
5
6
7
8
9

G3
3EN1[BA]

3EN2[AB]

1

2

logic diagram (positive logic)

1

DIR

18

17
16
15
14
13
12
11

B1

B2
B3
B4
B5
B6
B7
B8

A1

19

OE

2

18

B1

To Seven Other Channels

2

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UNIT

SN54LVTH245A, SN74LVTH245A

3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS130P – MAY 1992 – REVISED APRIL 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

†

Voltage range applied to any output in the high-impedance

or power-off state, V
Voltage range applied to any output in the high state, V
Current into any output in the low state, I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

: SN54LVTH245A 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(see Note 1) –0.5 V to V

O

CC

+ 0.5 V. . . . . . . . . . . . .

SN74LVTH245A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the high state, I

(see Note 2): SN54LVTH245A 48 mA. . . . . . . . . . . . . . . . . . . . . .

O

SN74LVTH245A 64 mA. . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Output clamp current, I
Package thermal impedance, θ

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

(see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 4)

SN54LVTH245A SN74LVTH245A

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V

T

A

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA

Power-up ramp rate 200 200 µs/V

CC

Operating free-air temperature –55 125 –40 85 °C

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

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3

SN54LVTH245A, SN74LVTH245A

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

3 V

V

V

V

V

V

V

Control inputs

‡

V

V

I

I(h

ld)

A or B orts

µA

V

CC

3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS130P – MAY 1992 – REVISED APRIL 1999

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LVTH245A SN74LVTH245A

MIN TYP†MAX MIN TYP†MAX

V

IK

OH

OL

I

I

A or B ports

I

off

o

I

OZPU

I

OZPD

I

CC

¶

∆I

CC

C

i

C

io

∗

On products compliant to MIL-PRF-38535, this parameter is not production tested.

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

Unused terminals are at VCC or GND.

§

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

¶

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

p

VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4

=

CC

= 2.7

CC

= 3

CC

VCC = 3.6 V, VI = VCC or GND ±1 ±1

p

VCC = 0 or 3.6 V, VI = 5.5 V 10 10

VCC = 3.6 V

VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

= 3

CC

VCC = 3.6 V§, VI = 0 to 3.6 V
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,

OE

= don’t care

VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE

= don’t care

=

= 3.6 V,
IO = 0,
VI = VCC or GND

VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND

VI = 3 V or 0 4 4 pF
VO = 3 V or 0 9 9 pF

IOH = –24 mA 2
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
IOL = 32 mA 0.5 0.5
IOL = 48 mA 0.55
IOL = 64 mA 0.55

VI = 5.5 V 20 20
VI = V

CC

VI = 0 –5 –5

VI = 0.8 V 75 75
VI = 2 V –75 –75

Outputs high 0.19 0.19
Outputs low 5 5
Outputs disabled 0.19 0.19

1 1

∗

±100

∗

±100

0.2 0.2 mA

µA

500

–750

±100 µA

±100 µA

mA

4

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A or B

B or A

ns

OE

A or B

ns

OE

A or B

ns

SN54LVTH245A, SN74LVTH245A

3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS130P – MAY 1992 – REVISED APRIL 1999

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

SN54LVTH245A SN74LVTH245A

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

†

All typical values are at VCC = 3.3 V, TA = 25°C.

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN TYP†MAX MIN MAX

0.7 3.7 4.2 1.2 2.3 3.5 4

0.7 3.7 4.2 1.2 2.1 3.5 4

1.2 5.7 7.4 1.3 3.2 5.5 7.1

1.6 5.7 6.8 1.7 3.4 5.5 6.5

1.8 6.2 6.8 2.2 3.5 5.9 6.5

1.8 5.3 5.5 2.2 3.4 5 5.1

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

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5

SN54LVTH245A, SN74LVTH245A

3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS130P – MAY 1992 – REVISED APRIL 1999

PARAMETER MEASUREMENT INFORMATION

S1

1.5 V

1.5 V

1.5 V1.5 V

500 Ω

t

w

1.5 V

500 Ω

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

t

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

t

PHL

t

PLH

6 V

Open

GND

2.7 V

0 V

V

OH

V

OL

V

OH

V

OL

2.7 V

0 V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

t

PZL

1.5 V

t

PZH

1.5 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Open

GND

1.5 V

t

6 V

h

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

t

PLZ

t

PHZ

2.7 V

0 V

2.7 V

0 V

2.7 V

0 V

3 V

V

OL

V

OH

≈ 0 V

Figure 1. Load Circuit and Voltage Waveforms

6

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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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semiconductor products or services might be or are used. TI’s publication of information regarding any third
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Copyright  1999, Texas Instruments Incorporated