3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130P – MAY 1992 – REVISED APRIL 1999
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical V
< 0.8 V at V
D
I
off
and Power-Up 3-State Support Hot
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
Insertion
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Packages, and Ceramic
(J) DIPs
description
CC
SN54LVTH245A...J OR W PACKAGE
SN74LVTH245A. . . DB, DW, OR PW PACKAGE
)
SN54LVTH245A. . . FK PACKAGE
A3
A4
A5
A6
A7
(TOP VIEW)
1
DIR
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
GND
10
(TOP VIEW)
A2A1DIR
3212019
4
5
6
7
8
10 11 12 13
9
A8
GND
B8
20
19
18
17
16
15
14
13
12
11
V
CC
B7
V
OE
B1
B2
B3
B4
B5
B6
B7
B8
18
17
16
15
14
B6OE
CC
B1
B2
B3
B4
B5
These octal bus transceivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
These devices are designed for asynchronous communication between data buses. They transmit data from
the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE
) input can be used to disable the devices so the buses are effectively isolated.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V
However, to ensure the high-impedance state above 1.5 V, OE
is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.
CC
should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I
and power-up 3-state. The I
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54L VTH245A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH245A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
circuitry
off
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LVTH245A, SN74LVTH245A
OPERATION
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130P – MAY 1992 – REVISED APRIL 1999
INPUTS
OEDIR
LLB data to A bus
LHA data to B bus
HXIsolation
FUNCTION TABLE
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OE
DIR
A1
A2
A3
A4
A5
A6
A7
A8
19
1
2
3
4
5
6
7
8
9
G3
3EN1[BA]
3EN2[AB]
1
2
logic diagram (positive logic)
1
DIR
18
17
16
15
14
13
12
11
B1
B2
B3
B4
B5
B6
B7
B8
A1
19
OE
2
18
B1
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
SN54LVTH245A, SN74LVTH245A
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130P – MAY 1992 – REVISED APRIL 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130P – MAY 1992 – REVISED APRIL 1999
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVTH245ASN74LVTH245A
PARAMETER
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
†
All typical values are at VCC = 3.3 V, TA = 25°C.
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MINMAXMINMAXMIN TYP†MAXMINMAX
0.73.74.21.22.33.54
0.73.74.21.22.13.54
1.25.77.41.33.25.57.1
1.65.76.81.73.45.56.5
1.86.26.82.23.55.96.5
1.85.35.52.23.455.1
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LVTH245A, SN74LVTH245A
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130P – MAY 1992 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
S1
1.5 V
1.5 V
1.5 V1.5 V
500 Ω
t
w
1.5 V
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
PHL
t
PLH
6 V
Open
GND
2.7 V
0 V
V
OH
V
OL
V
OH
V
OL
2.7 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TESTS1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Open
GND
1.5 V
t
6 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
t
PLZ
t
PHZ
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
≈ 0 V
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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