Datasheet SN74LVTH241DBR, SN74LVTH241DW, SN74LVTH241DWR, SN74LVTH241PWR Datasheet (Texas Instruments)

SN54LVTH241, SN74LVTH241

3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCAS352I – MARCH 1994 – REVISED APRIL 1999

D

State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation

D

Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With

3.3-V V

D

Support Unregulated Battery Operation

CC

)

Down to 2.7 V

D

Typical V
< 0.8 V at V

D

I

off

and Power-Up 3-State Support Hot

(Output Ground Bounce)

OLP

= 3.3 V, TA = 25°C

CC

Insertion

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Latch-Up Performance Exceeds 500 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) DIPs

description

SN54LVTH241...J PACKAGE

SN74LVTH241. . . DB, DW, OR PW PACKAGE

SN54LVTH241. . . FK PACKAGE

1A2
2Y3
1A3
2Y2
1A4

1OE

1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1

GND

4
5
6
7
8

9 10 11 12 13

(TOP VIEW)

1

20

2

19

3

18

4

17

5

16

6

15

7

14

8

13

9

12

10

11

(TOP VIEW)

CC

1A1

GND

V

1OE

2A1

1Y4

2Y4

3 2 1 20 19

2Y1

V

CC

2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1

2OE

18
17
16
15
14

2A2

1Y1
2A4
1Y2
2A3
1Y3

These octal buffers/drivers are designed specifically for low-voltage (3.3-V) VCC operation, with the capability
to provide a TTL interface to a 5-V system environment.

The ’L VTH241 devices are organized as two 4-bit line drivers with separate output-enable (1OE
When 1OE
1OE

is low or 2OE is high, the devices pass noninverted data from the A inputs to the Y outputs. When

is high or 2OE is low, the outputs are in the high-impedance state.

, 2OE) inputs.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V

However, to ensure the high-impedance state above 1.5 V, OE

is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.

CC

should be tied to VCC through a pullup resistor
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.

These devices are fully specified for hot-insertion applications using I

and power-up 3-state. The I

off

disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.

The SN54LVTH241 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH241 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Copyright  1999, Texas Instruments Incorporated

circuitry

off

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54LVTH241, SN74LVTH241

3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCAS352I – MARCH 1994 – REVISED APRIL 1999

FUNCTION TABLES

INPUTS

1OE 1A

L H H
L LL

HXZ

OUTPUT

1Y

INPUTS

2OE 2A

H H H
H LL

LXZ

logic symbol

1OE

1A1
1A2
1A3
1A4

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

1

2
4
6
8

EN

18
16
14
12

1Y1
1Y2
1Y3
1Y4

OUTPUT

2Y

2OE

2A1
2A2
2A3
2A4

logic diagram (positive logic)

1

1OE

2OE

19

11
13
15
17

19

EN

9

2Y1

7

2Y2

5

2Y3

3

2Y4

218

1A1

416

1A2

614

1A3

812

1A4

1Y1

1Y2

1Y3

1Y4

11 9

2A1

13 7

2A2

15 5

2A3

17 3

2A4

2Y1

2Y2

2Y3

2Y4

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

SN54LVTH241, SN74LVTH241

3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCAS352I – MARCH 1994 – REVISED APRIL 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

†

Voltage range applied to any output in the high-impedance

or power-off state, V
Voltage range applied to any output in the high state, V
Current into any output in the low state, I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

: SN54LVTH241 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(see Note 1) –0.5 V to V

O

CC

+ 0.5 V. . . . . . . . . . . . .

SN74LVTH241 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the high state, I

(see Note 2): SN54LVTH241 48 mA. . . . . . . . . . . . . . . . . . . . . . .

O

SN74LVTH241 64 mA. . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Output clamp current, I
Package thermal impedance, θ

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

(see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 4)

SN54LVTH241 SN74LVTH241

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V

T

A

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA

Power-up ramp rate 200 200 µs/V

CC

Operating free-air temperature –55 125 –40 85 °C

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54LVTH241, SN74LVTH241

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

3 V

V

V

V

V

V

V

I

A

Data inputs

V

V

V

V

I

I(hold)

Data in uts

µA

V

CC

3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCAS352I – MARCH 1994 – REVISED APRIL 1999

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LVTH241 SN74LVTH241

MIN TYP†MAX MIN TYP†MAX

V

IK

OH

OL

I

I

off

I

OZH

I

OZL

I

OZPU

I

OZPD

I

CC

∆I

CC

C

i

C

o

∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

Control inputs VCC = 3.6 V, VI = VCC or GND ±1 ±1

p

p

§

VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4

=

CC

= 2.7

CC

= 3

CC

VCC = 0 or 3.6 V, VI = 5.5 V 10 10

= 3.6

CC

VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

= 3

CC

VCC = 3.6 V‡, VI = 0 to 3.6 V
VCC = 3.6 V, VO = 3 V 5 5 µA

VCC = 3.6 V, VO = 0.5 V –5 –5 µA
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,

OE

/OE = don’t care

VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE

/OE = don’t care

=

= 3.6 V,
IO = 0,
VI = VCC or GND

VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND

VI = 3 V or 0 3 3 pF
VO = 3 V or 0 7 7 pF

IOH = –24 mA 2
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
IOL = 32 mA 0.5 0.5
IOL = 48 mA 0.55
IOL = 64 mA 0.55

VI = V

CC

VI = 0 –5 –5

VI = 0.8 V 75 75
VI = 2 V –75 –75

Outputs high 0.19 0.19
Outputs low 5 5
Outputs disabled 0.19 0.19

1 1

500

–750

∗

±100

∗

±100

0.2 0.2 mA

±100 µA

±100 µA

µ

mA

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

A

Y

ns

OE

OE

Y

ns

OE

OE

Y

ns

SN54LVTH241, SN74LVTH241

3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCAS352I – MARCH 1994 – REVISED APRIL 1999

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range, C

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

†

All typical values are at VCC = 3.3 V, TA = 25°C.

(INPUT)

= 50 pF (unless otherwise noted) (see Figure 1)

L

SN54LVTH241 SN74LVTH241

FROM

or

or

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN TYP†MAX MIN MAX

1 3.7 4 1.1 2.3 3.5 3.9

1.2 3.5 3.7 1.3 2.2 3.4 3.6
1 4.6 5.5 1.1 2.7 4.5 5.4

1.3 4.6 5.1 1.4 2.9 4.4 5

1.5 4.7 5.5 1.6 2.8 4.5 5.3

1.7 5 5.5 1.8 3 4.7 5.2

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54LVTH241, SN74LVTH241

3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCAS352I – MARCH 1994 – REVISED APRIL 1999

PARAMETER MEASUREMENT INFORMATION

6 V

From Output

Under Test

CL = 50 pF

(see Note A)

500 Ω

500 Ω

S1

GND

Open

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

6 V

GND

LOAD CIRCUIT

t

w

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

1.5 V

t

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

1.5 V

1.5 V

1.5 V1.5 V

t

PHL

t

PLH

2.7 V

0 V

2.7 V

0 V

V

OH

V

OL

V

OH

V

OL

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

1.5 V

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

t

PZL

1.5 V

t

PZH

1.5 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

t

h

1.5 V1.5 V

t

VOL + 0.3 V

t

VOH – 0.3 V

PLZ

PHZ

2.7 V

0 V

2.7 V

0 V

2.7 V

0 V

3 V

V

OL

V

OH

≈ 0 V

Figure 1. Load Circuit and Voltage Waveforms

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated