Datasheet SN74LVTH2245DBLE, SN74LVTH2245DBR, SN74LVTH2245DGVR, SN74LVTH2245DW, SN74LVTH2245DWR Datasheet (Texas Instruments)
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SN54LVTH2245, SN74LVTH2245
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS707C – SEPTEMBER 1997 – REVISED APRIL 1999
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
B-Port Outputs Have Equivalent 22-Ω
Series Resistors, So No External Resistors
Are Required
D
I
and Power-Up 3-State Support Hot
off
Insertion
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical V
< 0.8 V at V
D
Latch-Up Performance Exceeds 500 mA Per
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Packages, and Ceramic
(J) DIPs
CC
SN54LVTH2245...J OR W PACKAGE
SN74LVTH2245. . . DB, DW, OR PW PACKAGE
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
V
OE
B1
B2
B3
B4
B5
B6
B7
B8
CC
)
SN54LVTH2245. . . FK PACKAGE
A3
A4
A5
A6
A7
(TOP VIEW)
A2A1DIR
3212019
4
5
6
7
8
10 11 12 13
9
A8
V
B8
GND
CC
B7
18
17
16
15
14
B6 OE
B1
B2
B3
B4
B5
description
These octal bus transceivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
These devices are designed for asynchronous communication between data buses. They transmit data from
the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors
to reduce overshoot and undershoot.
When V
is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
) input can be used to disable the devices so the buses are effectively isolated.
should be tied to VCC through a pullup resistor;
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LVTH2245, SN74LVTH2245
OPERATION
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS707C – SEPTEMBER 1997 – REVISED APRIL 1999
description (continued)
These devices are fully specified for hot-insertion applications using I
and power-up 3-state. The I
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54L VTH2245 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH2245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation
logic symbol
†
OE
DIR
A1
A2
A3
A4
A5
A6
A7
A8
19
1
2
3
4
5
6
7
8
9
G3
3EN1[BA]
3EN2[AB]
1
18
B1
2
17
16
15
14
13
12
11
B2
B3
B4
B5
B6
B7
B8
circuitry
off
†
logic diagram (positive logic)
2
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1
DIR
2
A1
To Seven Other Channels
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19
18
OE
B1
UNIT
IOHHigh-level output current
mA
IOLLow-level output current
mA
SN54LVTH2245, SN74LVTH2245
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS707C – SEPTEMBER 1997 – REVISED APRIL 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high-impedance
or power-off state, V
Voltage range applied to any output in the high state, V
Current into any output in the low state, I
Current into any output in the high state, I
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
: SN54LVTH2245 (A port) 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 1) –0.5 V to V
O
SN74LVTH2245 (A port) 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . .
B port 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): SN54LVTH2245 (A port) 48 mA. . . . . . . . . . . . . . .
O
SN74LVTH2245 (A port) 64 mA. . . . . . . . . . . . . . .
B port 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
CC
+ 0.5 V. . . . . . . . . . . . .
†
recommended operating conditions (see Note 4)
SN54LVTH2245 SN74LVTH2245
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
p
p
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
A port –24 –32
B port –12 –12
A port 48 64
B port 12 12
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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3
SN54LVTH2245, SN74LVTH2245
PARAMETER
TEST CONDITIONS
UNIT
A port
V
VOHV
3 V
B port
V
V
V
A port
V
VOLV
V
B port
V
Control inputs
‡
V
V
I
I(hold)
A or B orts
µA
V
CC
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS707C – SEPTEMBER 1997 – REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH2245 SN74LVTH2245
MIN TYP†MAX MIN TYP†MAX
V
IK
p
p
p
p
I
I
A or B ports
I
off
p
I
OZPU
I
OZPD
I
CC
¶
∆I
CC
C
i
C
io
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
Unused terminals are at VCC or GND.
§
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4
=
CC
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 3 V, IOH = –12 mA 2 2
= 2.7
CC
= 3
CC
VCC = 2.7 V to 3.6 V, IOL = 100 µA 0.2 0.2
VCC = 3 V, IOL = 12 mA 0.8 0.8
VCC = 3.6 V, VI = VCC or GND ±1 ±1
p
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
VCC = 3.6 V
VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
= 3
CC
VCC = 3.6 V§, VI = 0 to 3.6 V
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE
= don’t care
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE
= don’t care
=
= 3.6 V,
IO = 0,
VI = VCC or GND
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = 3 V or 0 4 4 pF
VO = 3 V or 0 9 9 pF
IOH = –24 mA 2
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
IOL = 32 mA 0.5 0.5
IOL = 48 mA 0.55
IOL = 64 mA 0.55
VI = 5.5 V 20 20
VI = V
CC
VI = 0 –5 –5
VI = 0.8 V 75 75
VI = 2 V –75 –75
Outputs high 0.19 0.1 0.19
Outputs low 5 3 5
Outputs disabled 0.19 0.1 0.19
1 1
±100* ±100 µA
±100* ±100 µA
0.2 0.2 mA
µA
500
–750
mA
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
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A
B
ns
B
A
ns
OE
A
ns
OE
A
ns
OE
B
ns
OE
B
ns
SN54LVTH2245, SN74LVTH2245
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS707C – SEPTEMBER 1997 – REVISED APRIL 1999
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVTH2245 SN74LVTH2245
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
†
All typical values are at VCC = 3.3 V, TA = 25°C.
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
1 4.6 5.3 1.1 2.9 4.4 5.1
1 4.6 5.3 1.1 2.6 4.4 5.1
1 3.7 4.2 1.1 2.2 3.5 4
1 3.7 4.2 1.1 2 3.5 4
1.2 5.7 7.4 1.3 3.1 5.5 7.1
1.6 5.7 6.8 1.7 3.2 5.5 6.5
2 6.2 6.8 2.2 3.6 5.9 6.5
2 5.3 5.5 2.2 3.4 5 5.1
1.2 6.4 7.6 1.3 3.5 6.2 7.3
1.6 6.4 7.5 1.7 3.7 6.2 7.3
2 6.1 6.8 2.2 3.9 5.9 6.5
2 5.7 5.9 2.2 3.7 5.4 5.7
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LVTH2245, SN74LVTH2245
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS707C – SEPTEMBER 1997 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
S1
1.5 V
1.5 V
1.5 V1.5 V
500 Ω
t
w
1.5 V
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
PHL
t
PLH
6 V
Open
GND
2.7 V
0 V
V
OH
V
OL
V
OH
V
OL
2.7 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Open
GND
1.5 V
t
6 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
t
PLZ
t
PHZ
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
≈ 0 V
Figure 1. Load Circuit and Voltage Waveforms
6
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1999, Texas Instruments Incorporated
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