Texas Instruments SN74LVTH182652APM, SN74LVTH18652APM Datasheet
D
Members of the Texas Instruments
SCOPE
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art 3.3-V ABT Design Supports
Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V VCC)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Include D-Type Flip-Flops and Control
Circuitry to Provide Multiplexed
Transmission of Stored and Real-Time Data
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
B-Port Outputs of ’L VTH182652A Devices
Have Equivalent 25-Ω Series Resistors, So
No External Resistors Are Required
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
Family of Testability Products
Family
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
D
Compatible With the IEEE Std 1 149.1-1990
(JTAG) Test Access Port and
Boundary-Scan Architecture
D
SCOPE
– IEEE Std 1149.1-1990 Required
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
D
Packaged in 64-Pin Plastic Thin Quad Flat
(PM) Packages Using 0.5-mm
Center-to-Center Spacings and 68-Pin
Ceramic Quad Flat (HV) Packages Using
25-mil Center-to-Center Spacings
Instruction Set
Instructions and Optional CLAMP and
HIGHZ
From Outputs
description
The ’LVTH18652A and ’LVTH182652A scan test devices with 18-bit bus transceivers and registers are
members of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices
supports IEEE Std 1 149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan
access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed
transmission of data directly from the input bus or from the internal registers. They can be used either as two
9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot
samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating
the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers
and registers.
Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and
output-enable (OEAB and OEBA
registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation
to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus
(registered mode). When OEAB is high, the B outputs are active. When OEAB is low, the B outputs are in the
high-impedance state.
Control for B-to-A data flow is similar to that for A-to-B data flow but uses CLKBA, SBA, and OEBA inputs. Since
the OEBA
when OEBA is high. Figure 1 illustrates the four fundamental bus-management functions that can be performed
with the ’LVTH18652A and ’L VTH182652A.
input is active-low, the A outputs are active when OEBA is low and are in the high-impedance state
) inputs. For A-to-B data flow, data on the A bus is clocked into the associated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
description (continued)
In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs
other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the T AP interface.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The B-port outputs of ’L VTH182652A, which are designed to source or sink up to 12 mA, include equivalent 25-Ω
series resistors to reduce overshoot and undershoot.
The SN54LVTH18652A and SN54LVTH182652A are characterized for operation over the full military
temperature range of –55°C to 125°C. The SN74L VTH18652A and SN74LVTH182652A are characterized for
operation from –40°C to 85°C.
SN54LVTH18652A, SN54LVTH182652A. . . HV PACKAGE
(TOP VIEW)
1A2
1A1
1OEBA
GND
87 65493168672
10
1A3
11
1A4
12
1A5
1A6
1A7
1A8
1A9
NC
CC
2A1
2A2
2A3
2A4
2A5
2A6
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28 29
2A7
2A8
30
2A9
GND
GND
V
GND
NC – No internal connection
1SAB
1CLKAB
TDO
31 32 33 34
2SAB
2OEBA
2CLKAB
CC
VNCTMS
35 36 37 38 39
TDI
NC
1CLKBA
66 652764 63 62 61
CC
V
TCK
1SBA
1OEAB
GND
40 41 42 43
GND
2SBA
2CLKBA
1B1
1B2
2B9
2OEAB
1B3
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
2B8
1B4
1B5
1B6
GND
1B7
1B8
1B9
V
CC
NC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OPERATION OR FUNCTION
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
V
CC
2A1
2A2
2A3
GND
2A4
2A5
2A6
SN74LVTH18652A, SN74LVTH182652A. . . PM PACKAGE
1OEBA
1A1
GND
20
1A2
63 62 61 60 5964 58 56 55 5457
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18 19
(TOP VIEW)
1CLKAB
TDO
1SAB
21 22 23 24
CC
V
25 26 27 28 29
TMS
1CLKBA
1SBA
53 521751 50 49
1OEAB
GND
30 31 32
1B1
1B2
1B3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1B4
1B5
1B6
GND
1B7
1B8
1B9
V
CC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
CC
2A9
2A7
2A8
GND
2OEBA
FUNCTION TABLE
(normal mode, each 9-bit section)
INPUTS
OEAB OEBA CLKAB CLKBA SAB SBA A1–A9 B1–B9
L H L L X X Input disabled Input disabled Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ L X X Input Unspecified
H H ↑↑X
L X L ↑ X X Unspecified
L L ↑↑XX‡Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
L L X X X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H X X H X Input Output Stored A data to B bus
H L X X H H Output Output
†
The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
‡
Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
‡
X Input Output Store A in both registers
2SAB
2CLKAB
TDI
V
TCK
2CLKBA
DATA I/O
†
2B9
GND
2SBA
2B8
2OEAB
†
Input Hold A, store B
Stored A data to B bus and
stored B data to A bus
Store A, hold B
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
BUS A
OEAB
OEBA
LL
BUS A
CLKABXCLKBAXSABXSBA
REAL-TIME TRANSFER
BUS B TO BUS A
BUS B
L
BUS B
BUS A
OEAB OEBA
HH
BUS A
BUS B
CLKABXCLKBAXSABLSBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
OEAB
X
L
L
OEBA
CLKAB CLKBAXSABXSBA
H
X
H
STORAGE FROM
A, B, OR A AND B
↑
XX
↑
X
↑↑
X
X
X
OEAB OEBA
HL X HH
CLKAB CLKBA SAB SBA
X
TRANSFER STORED DA TA
TO A AND/OR B
Figure 1. Bus-Management Functions
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
functional block diagram
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
1OEAB
1OEBA
1CLKBA
1SBA
1CLKAB
1SAB
1A1
2OEAB
2OEBA
2CLKBA
2SBA
2CLKAB
2SAB
63
30
21
27
28
23
22
53
62
55
54
59
60
Boundary-Scan Register
V
CC
GND
C1
1D
51
C1
1D
One of Nine Channels
V
CC
GND
1B1
10
2A1
V
CC
24
TDI
V
CC
56
TMS
26
TCK
Pin numbers shown are for the PM package.
C1
1D
One of Nine Channels
Bypass Register
Boundary-Control
Register
Identification
Register
Instruction
Register
TAP
Controller
C1
1D
58
40
2B1
TDO
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
Terminal Functions
TERMINAL NAME DESCRIPTION
1A1–1A9,
2A1–2A9
1B1–1B9,
2B1–2B9
1CLKAB, 1CLKBA,
2CLKAB, 2CLKBA
GND Ground
1OEAB, 2OEAB
1OEBA, 2OEBA
1SAB, 1SBA,
2SAB, 2SBA
TCK
TDI
TDO
TMS
V
CC
Normal-function A-bus I/O ports. See function table for normal-mode logic.
Normal-function B-bus I/O ports. See function table for normal-mode logic.
Normal-function clock inputs. See function table for normal-mode logic.
Normal-function active-high output enables. See function table for normal-mode logic. An internal pulldown at each
terminal forces the terminal to a low level if left unconnected.
Normal-function active-low output enables. See function table for normal-mode logic. An internal pullup at each terminal
forces the terminal to a high level if left unconnected.
Normal-function select controls. See function table for normal-mode logic.
T est clock. One of four terminals required by IEEE Std 1149.1-1990. T est operations of the device are synchronous TCK.
Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.
T est data input. One of four terminals required by IEEE Std 1 149.1-1990. TDI is the serial input for shifting data through
the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
Test data output. One of four terminals required by IEEE Std 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.
Test mode select. One of four terminals required by IEEE Std 1149.1-1990. TMS directs the device through its TAP
controller states. An internal pullup forces TMS to a high level if left unconnected.
Supply voltage
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
test architecture
Serial-test information is conveyed by means of a 4-wire test bus or T AP that conforms to IEEE Std 1149.1-1990.
T est instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller
monitors two signals from the test bus, TCK and TMS. The T AP controller extracts the synchronization (TCK)
and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the
test structures in the device. Figure 2 shows the TAP-controller state diagram.
The T AP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Std 1 149.1-1990 4-wire test bus and boundary-scan architecture
and the relationship among the test bus, the T AP controller, and the test registers. As shown, the device contains
an 8-bit instruction register and four test-data registers: a 48-bit boundary-scan register, a 3-bit
boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register.
Test-Logic-Reset
TMS = H
TMS = L
TMS = L
Run-Test/Idle Select-DR-Scan
TMS = L
Capture-DR
TMS = L
Shift-DR
TMS = L
TMS = H
TMS = H
Exit1-DR
TMS = L
Pause-DR
TMS = L
TMS = H
Exit2-DR
TMS = H
Update-DR
TMS = HTMS = H
TMS = H TMS = H
TMS = L
TMS = L
Select-IR-Scan
TMS = H
TMS = L
Capture-IR
TMS = L
Shift-IR
TMS = L
TMS = H
TMS = H
Exit1-IR
TMS = L
Pause-IR
TMS = L
TMS = H
Exit2-IR
TMS = H
Update-IR
TMS = LTMS = H
Figure 2. TAP-Controller State Diagram
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TMS = LTMS = H
7
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
state diagram description
The T AP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram shown in Figure 2 is in accordance with IEEE Std 1 149.1-1990. The TAP controller proceeds
through its states based on the level of TMS at the rising edge of TCK.
As shown, the T AP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is defined as a state the T AP controller can retain for
consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the T est-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYP ASS instruction. Certain data
registers can also be reset to their power-up values.
The state machine is constructed such that the T AP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuited.
For the ’L VTH18652A and ’L VTH182652A, the instruction register is reset to the binary value 10000001, which
selects the IDCODE instruction. Bits 47–46 in the boundary-scan register are reset to logic 0 while bits 45–44
are reset to logic 1, ensuring that these cells, which control A-port and B-port outputs, are set to benign values
(i.e., such that if test mode were invoked the outputs would be at high-impedance state). Reset values of other
bits in the boundary-scan register should be considered indeterminate. The boundary-control register is reset
to the binary value 010, which selects the PSA test operation.
Run-Test/Idle
The T AP controller must pass through the Run-T est/Idle state (from T est-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test
operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the T AP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO, and on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least-significant bit of the selected data register.
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the T AP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling
edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, such update occurs
on the falling edge of TCK, following entry to the Update-DR state.
Capture-IR
When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK, upon which the T AP controller exits the Capture-IR state. For the ’L VTH18652A and
’LVTH182652A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO, and
on the first falling edge of TCK, TDO goes from the high-impedance state to the active state. TDO enables to
the logic level present in the least-significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the T AP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the
first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss
of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
register overview
With the exception of the bypass and device-identification registers, any test register can be thought of as a
serial-shift register with a shadow latch on each bit. The bypass and device identification registers differ in that
they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,
Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current
instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted
out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or
Update-DR), the shadow latches are updated from the shift register.
instruction register description
The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation
to be performed, which of the four data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.
Table 3 lists the instructions supported by the ’LVTH18652A and ’LVTH182652A. The even-parity feature
specified for SCOPE devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any
instructions that are defined for SCOPE devices but are not supported by this device default to BYPASS.
During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 3.
Bit 7
Parity
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
TDOTDI
Figure 3. Instruction Register Order of Scan
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
data register description
boundary-scan register
The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and
output data). The BSR is used 1) to store test data that is to be applied externally to the device output pins,
and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at
the device input pins.
The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR can change during Run-Test/Idle, as determined by the current instruction. At power up
or in Test-Logic-Reset, BSCs 47–46 are reset to logic 0 while BSCs 45–44 are reset to logic 1, ensuring that
these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked
the outputs would be at high-impedance state). Reset values of other BSCs should be considered
indeterminate.
The BSR order of scan is from TDI through bits 47–0 to TDO. T able 1 shows the BSR bits and their associated
device pin signals.
Table 1. Boundary-Scan Register Configuration
BSR BIT
NUMBER
47 2OEAB 35 2A9-I/O 17 2B9-I/O
46 1OEAB 34 2A8-I/O 16 2B8-I/O
45 2OEBA 33 2A7-I/O 15 2B7-I/O
44 1OEBA 32 2A6-I/O 14 2B6-I/O
43 2CLKAB 31 2A5-I/O 13 2B5-I/O
42 1CLKAB 30 2A4-I/O 12 2B4-I/O
41 2CLKBA 29 2A3-I/O 11 2B3-I/O
40 1CLKBA 28 2A2-I/O 10 2B2-I/O
39 2SAB 27 2A1-I/O 9 2B1-I/O
38 1SAB 26 1A9-I/O 8 1B9-I/O
37 2SBA 25 1A8-I/O 7 1B8-I/O
36 1SBA 24 1A7-I/O 6 1B7-I/O
–– –– 23 1A6-I/O 5 1B6-I/O
–– –– 22 1A5-I/O 4 1B5-I/O
–– –– 21 1A4-I/O 3 1B4-I/O
–– –– 20 1A3-I/O 2 1B3-I/O
–– –– 19 1A2-I/O 1 1B2-I/O
–– –– 18 1A1-I/O 0 1B1-I/O
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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