Datasheet SN74LVTH18502APM, SN74LVTH18502APMR, SN74LVTH182502APM, SNJ54LVTH18502AHV Datasheet (Texas Instruments)

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SCOPE

Members of the Texas Instruments

Widebus

State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V

Support Unregulated Battery Operation Down to 2.7 V

UBT

Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode

Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors

B-Port Outputs of ’LVTH182502A Devices Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

 Family of Testability Products

 Family

 (Universal Bus Transceiver)

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture

SCOPE

– IEEE Standard 1149.1-1990 Required

)

– Parallel-Signature Analysis at Inputs – Pseudorandom Pattern Generation From

– Sample Inputs/Toggle Outputs – Binary Count From Outputs – Device Identification – Even-Parity Opcodes

Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

 Instruction Set

Instructions and Optional CLAMP and HIGHZ

Outputs

description

The ’LVTH18502A and ’L VTH182502A scan test devices with 18-bit universal bus transceivers are members of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE Standard 1 149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) V capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.

Data flow in each direction is controlled by output-enable (OEAB and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low , the A-bus data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB B outputs are active. When OEAB similar to A-to-B data flow, but uses the OEBA

In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

is high, the B outputs are in the high-impedance state. B-to-A data flow is

, LEBA, and CLKBA inputs.

and OEBA), latch-enable (LEAB and LEBA),

operation, but with the

is low, the

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

description (continued)

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the T AP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The B-port outputs of ’L VTH182502A, which are designed to source or sink up to 12 mA, include 25- Ω series

resistors to reduce overshoot and undershoot. The SN54LVTH18502A and SN54LVTH182502A are characterized for operation over the full military

temperature range of –55°C to 125°C. The SN74L VTH18502A and SN74LVTH182502A are characterized for operation from –40°C to 85°C.

SN54LVTH18502A, SN54LVTH182502A. . . HV PACKAGE

1A2

1A1

1OEAB

GND

1LEAB

1CLKAB

(TOP VIEW)

VNCTMS

TDO

1CLKBA

1LEBA

1OEBA

GND

1B1

1B2

1B3

87 65493168672

1A3 1A4 1A5

GND

1A6 1A7 1A8 1A9

2A1 2A2 2A3

GND

2A4 2A5 2A6

10 11 12 13 14 15 16 17

18 19

20 21 22 23 24 25 26

28 29 30 31 32 33 34

2A9

2A7

2A8

NC – No internal connection

GND

2LEAB

2OEAB

35 36 37 38 39

TDI

2CLKAB

66 652764 63 62 61

TCK

2LEBA

2CLKBA

40 41 42 43

2B9

GND

2OEBA

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

2B8

1B4 1B5 1B6 GND 1B7 1B8 1B9 V

NC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7

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3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

1A3 1A4 1A5

GND

1A6 1A7 1A8 1A9

2A1 2A2 2A3

GND

2A4 2A5 2A6

SN74LVTH18502A, SN74LVTH182502A. . . PM PACKAGE

1OEAB

1A1

GND

1A2

63 62 61 60 5964 58 56 55 5457 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

18 19

(TOP VIEW)

1CLKAB

TDO

1LEAB

21 22 23 24

25 26 27 28 29

TMS

1CLKBA

1LEBA

53 52

1OEBA

GND

51 50 49

30 31 32

1B1

1B2

1B3

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

1B4 1B5 1B6 GND 1B7 1B8 1B9 V

2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7

2LEAB

2CLKAB

TDI

TCK

2CLKBA

†

GND

2LEBA

OUTPUT

2OEBA

‡

2A9

2A7

2A8

GND

2OEAB

FUNCTION TABLE

(normal mode, each register)

INPUTS

OEAB LEAB CLKAB A

L L L X B L L ↑ LL LL↑HH LHXLL LHXHH

HXXXZ

†

A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA

‡

Output level before the indicated steady-state input conditions are established

, LEBA, and CLKBA.

2B9

2B8

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SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

functional block diagram

1LEAB

1CLKAB

1OEAB

1LEBA

1CLKBA

1OEBA

1A1

2LEAB

2CLKAB

2OEAB

2LEBA

62 54

One of Nine Channels

21 28

Boundary-Scan Register

C1 1D

1B1

2A1

TDI

TMS TCK

2CLKBA

2OEBA

Pin numbers shown are for the PM package.

One of Nine Channels

Bypass Register

Boundary-Control

Identification

Instruction

TAP

Controller

C1 1D

2B1

TDO

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SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

Terminal Functions

TERMINAL NAME DESCRIPTION

1A1–1A9,

2A1–2A9

1B1–1B9,

2B1–2B9

1CLKAB, 1CLKBA,

2CLKAB, 2CLKBA

GND Ground

1LEAB, 1LEBA, 2LEAB, 2LEBA

1OEAB, 1OEBA,

2OEAB

, 2OEBA

TCK

TDI

TDO

TMS V

Normal-function A-bus I/O ports. See function table for normal-mode logic.

Normal-function B-bus I/O ports. See function table for normal-mode logic.

Normal-function clock inputs. See function table for normal-mode logic.

Normal-function latch enables. See function table for normal-mode logic. Normal-function output enables. See function table for normal-mode logic. An internal pullup at each terminal forces the

terminal to a high level if left unconnected. T est clock. One of four terminals required by IEEE Standard 1149.1-1990. T est operations of the device are synchronous

to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. Test data input. One of four terminals required by IEEE Standard 1 149.1-1990. TDI is the serial input for shifting data

through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected. T est data output. One of four terminals required by IEEE Standard 1 149.1-1990. TDO is the serial output for shifting data

through the instruction register or selected data register. T est mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its T AP

controller states. An internal pullup forces TMS to a high level if left unconnected. Supply voltage

3.3-V ABT SCAN TEST DEVICES

SCBS668B – JULY 1996 – REVISED MARCH 1999

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SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

test architecture

Serial-test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Standard 1 149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The T AP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully one-half of the TCK cycle.

The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship among the test bus, the T AP controller, and the test registers. As shown, the device contains an 8-bit instruction register and four test-data registers: a 48-bit boundary-scan register, a 3-bit boundary-control register, a 1-bit bypass register, and a 32-bit device identification register.

Test-Logic-Reset

TMS = H

TMS = L

Run-Test/Idle Select-DR-Scan

TMS = L

Capture-DR

TMS = L

Shift-DR

TMS = L

TMS = H

Exit1-DR

TMS = L

Pause-DR

TMS = L

TMS = H

Exit2-DR

TMS = H

TMS = HTMS = H

TMS = H TMS = H

TMS = L

Select-IR-Scan

TMS = H

TMS = L

Capture-IR

TMS = L

Shift-IR

TMS = L

TMS = H

Exit1-IR

TMS = L

Pause-IR

TMS = L

TMS = H

Exit2-IR

TMS = H

Update-DR

TMS = LTMS = H

Update-IR

TMS = LTMS = H

Figure 1. TAP-Controller State Diagram

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SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

state diagram description

The TAP controller is a synchronous finite-state machine that provides test control signals throughout the device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK.

As shown, the T AP controller consists of 16 states. There are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. A stable state is a state the T AP controller can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the T est-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYP ASS instruction. Certain data registers can also be reset to their power-up values.

The state machine is constructed such that the T AP controller returns to the Test-Logic-Reset state in no more than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left unconnected or if a board defect causes it to be open circuited.

For the ’L VTH18502A and ’L VTH182502A, the instruction register is reset to the binary value 10000001, which selects the IDCODE instruction. Bits 47–44 in the boundary-scan register are reset to logic 1, ensuring that these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked the outputs would be at the high-impedance state). Reset-value of other bits in the boundary-scan register should be considered indeterminate. The boundary-control register is reset to the binary value 010, which selects the PSA test operation.

Run-T est/Idle

The T AP controller must pass through the Run-T est/Idle state (from T est-Logic-Reset) before executing any test operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans. Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test operations selected by the boundary-control register are performed while the TAP controller is in the Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the T AP controller exits either of these states on the next TCK cycle. These states allow the selection of either data-register scan or instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR state, the selected data register can capture a data value as specified by the current instruction. Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the Capture-DR state.

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3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the selected data register.

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the TCK cycle in which the T AP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, such update occurs on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In the Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the rising edge of TCK, upon which the T AP controller exits the Capture-IR state. For the ’L VTH18502A and ’LVTH182502A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO. On the first falling edge of TCK, TDO goes from the high-impedance state to the active state. TDO enables to the logic level present in the least-significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). The last shift occurs on the rising edge of TCK, upon which the T AP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss of data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK, following entry to the Update-IR state.

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SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

With the exception of the bypass and device-identification registers, any test register can be thought of as a serial shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the four data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

Table 3 lists the instructions supported by the ’LVTH18502A and ’LVTH182502A. The even-parity feature specified for SCOPE devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are defined for SCOPE devices but are not supported by this device default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 2.

Bit 7 Parity (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0

(LSB)

TDOTDI

Figure 2. Instruction Register Order of Scan

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3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

data register description

boundary-scan register

The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and output data). The BSR is used 1) to store test data that is to be applied externally to the device output pins, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input pins.

The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or in T est-Logic-Reset, BSCs 47–44 are reset to logic 1, ensuring that these cells, which control A-port and B-port outputs are set to benign values (i.e., if test mode were invoked, the outputs would be at the high-impedance state). Reset values of other BSCs should be considered indeterminate.

The BSR order of scan is from TDI through bits 47–0 to TDO. T able 1 shows the BSR bits and their associated device pin signals.

Table 1. Boundary-Scan Register Configuration

BSR BIT

NUMBER

47 2OEAB 35 2A9-I/O 17 2B9-I/O 46 1OEAB 34 2A8-I/O 16 2B8-I/O 45 2OEBA 33 2A7-I/O 15 2B7-I/O 44 1OEBA 32 2A6-I/O 14 2B6-I/O 43 2CLKAB 31 2A5-I/O 13 2B5-I/O 42 1CLKAB 30 2A4-I/O 12 2B4-I/O 41 2CLKBA 29 2A3-I/O 11 2B3-I/O 40 1CLKBA 28 2A2-I/O 10 2B2-I/O 39 2LEAB 27 2A1-I/O 9 2B1-I/O

38 1LEAB 26 1A9-I/O 8 1B9-I/O 37 2LEBA 25 1A8-I/O 7 1B8-I/O 36 1LEBA 24 1A7-I/O 6 1B7-I/O –– –– 23 1A6-I/O 5 1B6-I/O –– –– 22 1A5-I/O 4 1B5-I/O –– –– 21 1A4-I/O 3 1B4-I/O –– –– 20 1A3-I/O 2 1B3-I/O –– –– 19 1A2-I/O 1 1B2-I/O –– –– 18 1A1-I/O 0 1B1-I/O

DEVICE SIGNAL

BSR BIT

NUMBER

DEVICE SIGNAL

BSR BIT

NUMBER

DEVICE SIGNAL

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3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

boundary-control register

The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run test (RUNT) instruction to implement additional test operations not included in the basic SCOPE instruction set. Such operations include PRPG, PSA, and binary count up (COUNT). Table 4 shows the test operations that are decoded by the BCR.

During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is reset to the binary value 010, which selects the PSA test operation. The BCR order of scan is shown in Figure 3.

Bit 2

(MSB)

Bit 1

Bit 0

(LSB)

TDOTDI

Figure 3. Boundary-Control Register Order of Scan

bypass register

The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path, reducing the number of bits per test pattern that must be applied to complete a test operation. During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4.

Bit 0

TDOTDI

Figure 4. Bypass Register Order of Scan

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SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

device-identification register

The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer, part number, and version of this device.

For the ’LVTH18502A, the binary value 00110000000000011100000000101111 (3001C02F, hex) is captured (during Capture-DR state) in the IDR to identify this device as Texas Instruments SN54/74LVTH18502A.

For the ’L VTH182502A, the binary value 001 10000000000100001000000101111 (3002102F , hex) is captured (during Capture-DR state) in the device-identification register to identify this device as Texas Instruments SN54/74LVTH182502A.

The IDR order of scan is from TDI through bits 31–0 to TDO. T able 2 shows the IDR bits and their significance.

Table 2. Device-Identification Register Configuration

IDR BIT

NUMBER

31 VERSION3 27 PARTNUMBER15 11 MANUFACTURER10 30 VERSION2 26 PARTNUMBER14 10 MANUFACTURER09 29 VERSION1 25 PARTNUMBER13 9 MANUFACTURER08 28 VERSION0 24 PARTNUMBER12 8 MANUFACTURER07 –– –– 23 PARTNUMBER11 7 MANUFACTURER06 –– –– 22 PARTNUMBER10 6 MANUFACTURER05 –– –– 21 PARTNUMBER09 5 MANUFACTURER04 –– –– 20 PARTNUMBER08 4 MANUFACTURER03 –– –– 19 PARTNUMBER07 3 MANUFACTURER02 –– –– 18 PARTNUMBER06 2 MANUFACTURER01 –– –– 17 PARTNUMBER05 1 MANUFACTURER00 –– –– 16 PARTNUMBER04 0 LOGIC1 –– –– 15 PARTNUMBER03 –– –– –– –– 14 PARTNUMBER02 –– –– –– –– 13 PARTNUMBER01 –– –– –– –– 12 PARTNUMBER00 –– ––

†

Note that for TI products, bits 11–0 of the device-identification register always contain the binary value 000000101111 (02F, hex).

IDENTIFICATION

SIGNIFICANCE

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

†

† † † † † † † † † † †

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

instruction-register opcode description

The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each instruction.

Table 3. Instruction-Register Opcodes

BINARY CODE

BIT 7 → BIT 0

MSB → LSB

00000000 EXTEST Boundary scan Boundary scan Test 10000001 IDCODE Identification read Device identification Normal 10000010 SAMPLE/PRELOAD Sample boundary Boundary scan Normal 0000001 1 BYPASS 10000100 BYPASS 00000101 BYPASS 00000110 HIGHZ Control boundary to high impedance Bypass Modified test 100001 11 CLAMP Control boundary to 1/0 Bypass Test 10001000 BYPASS 00001001 RUNT Boundary-run test Bypass Test 00001010 READBN Boundary read Boundary scan Normal 1000101 1 READBT Boundary read Boundary scan Test 00001 100 CELLTST Boundary self test Boundary scan Normal 10001 101 TOPHIP Boundary toggle outputs Bypass Test 10001 110 SCANCN Boundary-control register scan Boundary control Normal

00001 111 SCANCT Boundary-control register scan Boundary control Test All others BYP ASS Bypass scan Bypass Normal

†

Bit 7 is used to maintain even parity in the 8-bit instruction.

‡

The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the ’LVTH18502A or ’LVTH182502A.

†

SCOPE OPCODE DESCRIPTION

‡ ‡ ‡

‡

SELECTED DATA

Bypass scan Bypass Normal Bypass scan Bypass Normal Bypass scan Bypass Normal

Bypass scan Bypass Normal

MODE

boundary scan

This instruction conforms to the IEEE Standard 1 149.1-1990 EXTEST instruction. The BSR is selected in the scan path. Data appearing at the device input and I/O pins is captured in the associated BSCs. Data that has been scanned into the I/O BSCs for pins in the output mode is applied to the device I/O pins. Data present at the device pins, except for output enables, is passed through the BSCs to the normal on-chip logic. For I/O pins, the operation of a pin as input or output is determined by the contents of the output-enable BSCs (bits 47–44 of the BSR). When a given output enable is active (logic 0), the associated I/O pins operate in the output mode. Otherwise, the I/O pins operate in the input mode. The device operates in the test mode.

identification read

This instruction conforms to the IEEE Standard 1149.1-1990 IDCODE instruction. The IDR is selected in the scan path. The device operates in the normal mode.

sample boundary

This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is selected in the scan path. Data appearing at the device input pins and I/O pins in the input mode is captured in the associated BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the BSCs associated with I/O pins in the output mode. The device operates in the normal mode.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

bypass scan

This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the normal mode.

control boundary to high impedance

This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device input pins remain operational, and the normal on-chip logic function is performed.

control boundary to 1/0

This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the I/O BSCs for pins in the output mode is applied to the device I/O pins. The device operates in the test mode.

boundary-run test

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during Run-Test /Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP), PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up (PSA/COUNT).

boundary read

The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This instruction is useful for inspecting data after a PSA operation.

boundary self test

The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR. In this way , the contents of the shadow latches can be read out to verify the integrity of both shift-register and shadow-latch elements of the BSR. The device operates in the normal mode.

boundary toggle outputs

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising edge of TCK in Run-Test/Idle and is then updated in the shadow latches and applied to the associated device I/O pins on each falling edge of TCK in Run-Test/Idle. Data in the input-mode BSCs remains constant. Data appearing at the device input or I/O pins is not captured in the input-mode BSCs. The device operates in the test mode.

boundary-control-register scan

The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This operation must be performed before a boundary-run test operation to specify which test operation is to be executed.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

boundary-control-register opcode description

The BCR opcodes are decoded from BCR bits 2–0, as shown in Table 4. The selected test operation is performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms.

Table 4. Boundary-Control Register Opcodes

BINARY CODE

BIT 2 → BIT 0

MSB → LSB

X00 Sample inputs/toggle outputs (TOPSIP) X01 Pseudorandom pattern generation/36-bit mode (PRPG) X10 Parallel-signature analysis/36-bit mode (PSA)

011 Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG) 111 Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)

While the control input BSCs (bits 47–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms, the output-enable BSCs (bits 47–44 of the BSR) control the drive state (active or high impedance) of the selected device output pins. These BCR instructions are only valid when both bytes of the device are operating in one direction of data flow (i.e., 1OEAB 1OEAB

= 2OEAB and 1OEBA = 2OEBA). Otherwise, the bypass instruction is operated.

≠ 1OEBA and 2OEAB ≠ 2OEBA) and in the same direction of data flow (i.e.,

DESCRIPTION

sample inputs/toggle outputs (TOPSIP)

Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling edge of TCK.

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3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

pseudorandom pattern generation (PRPG)

A pseudorandom pattern is generated in the shift-register elements of the selected BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each falling edge of TCK. Figures 5 and 6 show the 36-bit linear-feedback shift-register algorithms through which the patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes does not produce additional patterns.

2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A8-I/O2A9-I/O

1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A8-I/O1A9-I/O

2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B9-I/O

1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B9-I/O

Figure 5. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)

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SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B8-I/O2B9-I/O

1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B8-I/O1B9-I/O

2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A9-I/O

1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A9-I/O

Figure 6. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)

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SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

parallel-signature analysis (PSA)

Data appearing at the selected device input-mode I/O pins is compressed into a 36-bit parallel signature in the shift-register elements of the selected BSCs on each rising edge of TCK. Data in the shadow latches of the selected output-mode BSCs remains constant and is applied to the associated device I/O pins. Figures 7 and 8 show the 36-bit linear-feedback shift-register algorithms through which the signature is generated. An initial seed value should be scanned into the BSR before performing this operation.

2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A8-I/O2A9-I/O

1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A8-I/O1A9-I/O

2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B9-I/O

1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B9-I/O

Figure 7. 36-Bit PSA Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)

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SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B8-I/O2B9-I/O

1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B8-I/O1B9-I/O

2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A9-I/O

1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A9-I/O

Figure 8. 36-Bit PSA Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

simultaneous PSA and PRPG (PSA/PRPG)

Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an 18-bit pseudorandom pattern is generated in the shift-register elements of the selected output-mode BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling edge of TCK. Figures 9 and 10 show the 18-bit linear-feedback shift-register algorithms through which the signature and patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes does not produce additional patterns.

2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A8-I/O2A9-I/O

1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A8-I/O1A9-I/O

2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B9-I/O

1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B9-I/O

Figure 9. 18-Bit PSA/PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B8-I/O2B9-I/O

1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B8-I/O1B9-I/O

2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A9-I/O

1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A9-I/O

Figure 10. 18-Bit PSA/PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

simultaneous PSA and binary count up (PSA/COUNT)

Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an 18-bit binary count-up pattern is generated in the shift-register elements of the selected output-mode BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling edge of TCK. Figures 1 1 and 12 show the 18-bit linear-feedback shift-register algorithms through which the signature is generated. An initial seed value should be scanned into the BSR before performing this operation.

2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A8-I/O2A9-I/O

1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A8-I/O1A9-I/O

MSB

2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B9-I/O

LSB

1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B9-I/O

Figure 11. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B8-I/O2B9-I/O

1B9-I/O

MSB

2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A9-I/O

1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A9-I/O

1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B8-I/O

LSB

Figure 12. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

timing description

All test operations of the ’L VTH18502A and ’LVTH182502A are synchronous to the TCK signal. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling edge of TCK. The TAP controller is advanced through its states (as shown in Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge to TCK.

A simple timing example is shown in Figure 13. In this example, the TAP controller begins in the Test-Logic-Reset state and is advanced through its states, as necessary, to perform one instruction-register scan and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 5 details the operation of the test circuitry during each TCK cycle.

Table 5. Explanation of Timing Example

TCK

CYCLE(S)

1 Test-Logic-Reset 2 Run-Test/Idle

3 Select-DR-Scan 4 Select-IR-Scan

5 Capture-IR

6 Shift-IR

7–13 Shift-IR

14 Exit1-IR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. 15 Update-IR The IR is updated with the new instruction (BYPASS) on the falling edge of TCK. 16 Select-DR-Scan

17 Capture-DR

18 Shift-DR

19–20 Shift-DR The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.

21 Exit1-DR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. 22 Update-DR The selected data register is updated with the new data on the falling edge of TCK. 23 Select-DR-Scan 24 Select-IR-Scan 25 Test-Logic-Reset T est operation completed

TAP STATE

AFTER TCK

DESCRIPTION

TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward the desired state.

The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the Capture-IR state.

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state.

One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value 11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.

The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the Capture-DR state.

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ООООО

TCK

TMS

TDO

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

TDI

TAP

Controller

State

Run-Test/Idle

Test-Logic-Reset

Select-DR-Scan

Capture-IR

Select-IR-Scan

Shift-IR

3-State (TDO) or Don’t Care (TDI)

Exit1-IR

Update-IR

Capture-DR

Select-DR-Scan

Shift-DR

Exit1-DR

Update-DR

Select-IR-Scan

Select-DR-Scan

Figure 13. Timing Example

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range, V Voltage range applied to any output in the high state or power-off state, V Current into any output in the low state, I

Current into any output in the high state, I

Input clamp current, I Output clamp current, I Package thermal impedance, θ Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.

2. This current only flows when the output is in the high state and VO > VCC.

3. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

: SN54LVTH18502A 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 1) –0.5 V to 7 V. . . .

SN54LVTH182502A (A port or TDO) 96 mA. . . . . . . . . . . . . . . . .

SN54LVTH182502A (B port) 30 mA. . . . . . . . . . . . . . . . . . . . . . . .

SN74LVTH18502A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74LVTH182502A (A port or TDO) 128 mA. . . . . . . . . . . . . . . .

SN74LVTH182502A (B port) 30 mA. . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): SN54LVTH18502A 48 mA. . . . . . . . . . . . . . . . . . . .

SN54LVTH182502A (A port or TDO) 48 mA. . . .

SN54LVTH182502A (B port) 30 mA. . . . . . . . . . .

SN74LVTH18502A 64 mA. . . . . . . . . . . . . . . . . . . .

SN74LVTH182502A (A port or TDO) 64 mA. . . .

SN74LVTH182502A (B port) 30 mA. . . . . . . . . . .

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 3): PM package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Test-Logic-Reset

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

UNIT

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

recommended operating conditions (see Note 4)

SN54LVTH18502A SN74LVTH18502A

MIN MAX MIN MAX

V V V V I

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V T

†

Current duty cycle ≤ 50%, f ≥ 1 kHz

NOTE 4: All unused CLK, LE, or TCK inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI

Supply voltage 2.7 3.6 2.7 3.6 V

High-level input voltage 2 2 V

Low-level input voltage 0.8 0.8 V

Input voltage 5.5 5.5 V

High-level output current –24 –32 mA Low-level output current 24 32 mA

†

Low-level output current 48 64 mA

Operating free-air temperature –55 125 –40 85 °C

application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

UNIT

3 V

CLK,

TMS

‡

orts

‡

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

SN54LVTH18502A SN74LVTH18502A

MIN TYP†MAX MIN TYP†MAX

CLK LE, TCK

OE, TDI,

A or B p

off

I(hold)

OZH

OZL

OZPU

OZPD

∆I

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

Unused pins at VCC or GND

The parameter I

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

A or B ports

TDO VCC = 3.6 V, VO = 3 V 1 1 µA TDO VCC = 3.6 V, VO = 0.5 V –1 –1 µA TDO VCC = 0 to 1.5 V, VO = 0.5 V or 3 V ±50 ±50 µA TDO VCC = 1.5 V to 0, VO = 0.5 V or 3 V ±50 ±50 µA

I(hold)

VCC = 2.7 V, II = –18 mA –1.2 –1.2 V VCC = 2.7 V to 3.3 V, IOH = –100 µA VCC–0.2 VCC–0.2 VCC = 2.7 V, IOH = –3 mA 2.4 2.4

IOH = –8 mA 2.4 2.4

VCC = 3 V

= 2.7

VCC = 3.6 V, VI = VCC or GND ±1 ±1 VCC = 0 or 3.6 V, VI = 5.5 V 10 10

VCC = 3.6 V

VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

= 3

= 3.6 V, IO = 0, VI = VCC or GND

VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND

VI = 3 V or 0 4 4 pF VO = 3 V or 0 10 10 pF VO = 3 V or 0 8 8 pF

includes the off-state output leakage current.

IOH = –24 mA 2 IOH = –32 mA 2 IOL = 100 µA 0.2 0.2 IOL = 24 mA 0.5 0.5 IOL = 16 mA 0.4 0.4 IOL = 32 mA 0.5 0.5 IOL = 48 mA 0.55 IOL = 64 mA 0.55

VI = 5.5 V 5 5 VI = V

VI = 0 –25 –100 –25 –100 VI = 5.5 V 20 20 VI = V

VI = 0 –5 –5

VI = 0.8 V 75 500 75 150 500 VI = 2 V –75 –500 –75 –150 –500

Outputs high 0.6 3 0.6 2 Outputs low 18 30 18 24 Outputs disabled 0.6 3 0.6 2

1 1

0.5 0.5 mA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

twPulse duration

A before LEAB↓ or

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

timing requirements over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14)

SN54LVTH18502A SN74LVTH18502A

clock

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAX

Clock frequency CLKAB or CLKBA 0 100 0 80 0 100 0 80 MHz

CLKAB or CLKBA high or low 4.6 5.8 4.4 5.6 LEAB or LEBA high 3.2 3.2 3 3

Setup time

Hold time

A before CLKAB↑ or B before CLKBA↑

A before LEAB↓ or B before LEBA↓

A after CLKAB↑ or B after CLKBA↑

A after LEAB↓ or B after LEBA↓ 3.4 4.2 3.1 3.5

CLK high 1.6 1.1 1.5 0.7 CLK low 1.8 1.8 1.6 1.6

3 3.2 2.8 3

1.4 1.1 1.4 1.1

VCC = 2.7 V

timing requirements over recommended operating free-air temperature range (unless otherwise noted) (test mode) (see Figure 14)

SN54LVTH18502A SN74LVTH18502A

clock

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAX

Clock frequency TCK 0 50 0 40 0 50 0 40 MHz Pulse duration TCK high or low 9.5 10.5 9.5 10.5 ns

A, B, CLK, LE, or OE

Setup time

Hold time

Delay time Power up to TCK↑ 50 50 50 50 ns Rise time VCC power up 1 1 1 1 µs

before TCK↑ TDI before TCK↑ TMS before TCK↑ 2.5 3.5 2.5 3.5 A, B, CLK, LE, or OE

after TCK↑ TDI after TCK↑ TMS after TCK↑ 1.5 1 1.5 1

6.7 7.1 6.5 7

2.5 3.5 2.5 3.5

1.5 1 1.5 1

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

A or B

B or A

CLKAB or CLKBA

B or A

LEAB or LEBA

B or A

OEAB

OEBA

B or A

OEAB or OEBA

B or A

TCK↓

A or B

TCK↓

TDO

TCK↓

A or B

TCK↓

TDO

TCK↓

A or B

TCK↓

TDO

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14)

SN54LVTH18502A SN74LVTH18502A

PARAMETER

max

PLH

PHL

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

FROM

(INPUT)

CLKAB or CLKBA 100 80 100 80 MHz

(OUTPUT)

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.1 5.1 5.8 1.5 4.9 5.6

1.3 5.2 5.8 1.5 4.9 5.6

1.1 6.7 7.2 1.5 5.8 6.8

1.5 6.7 7.2 1.5 5.8 6.8

1.5 7.8 9.3 1.5 7.4 8.4

1.3 6.7 7 1.5 5.7 6.4 1 8.2 8.8 1.5 7.1 8.3

1.5 8.1 9.1 1.5 7.1 8.3

2.3 9.3 10 2.5 7.8 8.4 2 9 9.2 2.5 7.8 8.4

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (test mode) (see Figure 14)

SN54LVTH18502A SN74LVTH18502A

PARAMETER

max

PLH

PHL

PLH

PHL

PZH

PZL

PZH

PZL

PHZ

PLZ

PHZ

PLZ

FROM

(INPUT)

TCK 50 40 50 40 MHz

(OUTPUT)

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.6 15 18 2.5 14 17

2.5 15 18 2.5 14 17 1 6 7 1 5.5 6.5 1 8 9 1.5 6.5 7.5 3 19 21 4 17 20

3.2 18 21 4 17 20 1 6 7 1 5.5 6.5

1.5 6 7 1.5 5.5 6.5

2.6 19 21 4 18 20

3.6 18 19.5 4 17 18.5

1.5 7.5 9 1.5 7 8.5

1.5 7.5 8.5 1.5 7 8

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

UNIT

IOHHigh-level output current

IOLLow-level output current

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

recommended operating conditions (see Note 4)

SN54LVTH182502A SN74LVTH182502A

MIN MAX MIN MAX

V V V V

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V T

†

Current duty cycle ≤ 50%, f ≥ 1 kHz

NOTE 1: All unused CLK, LE, or TCK inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI

Supply voltage 2.7 3.6 2.7 3.6 V

High-level input voltage 2 2 V

Low-level input voltage 0.8 0.8 V

Input voltage 5.5 5.5 V

†

Low-level output current A port, TDO 48 64 mA

Operating free-air temperature –55 125 –40 85 °C

application report,

Implications of Slow or Floating CMOS Inputs

A port, TDO –24 –32 B port –12 –12 A port, TDO 24 32 B port 12 12

, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

UNIT

TDO

CLK,

TDI, TMS

‡

orts

‡

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

SN54LVTH182502A SN74LVTH182502A

MIN TYP†MAX MIN TYP†MAX

A, B, TDO VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2

off

I(hold)

OZH

OZL

OZPU

OZPD

∆I

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

Unused pins at VCC or GND

The parameter I

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

A port, TDO

B port VCC = 3 V, IOH = –12 mA 2 2 A, B, TDO VCC = 2.7 V, IOL = 100 µA 0.2 0.2

A port,

B port VCC = 3 V, IOL = 12 mA 0.8 0.8 CLK

LE, TCK

OE,

A or B p

A or B ports

TDO VCC = 3.6 V, VO = 3 V 1 1 µA TDO VCC = 3.6 V, VO = 0.5 V –1 –1 µA TDO VCC = 0 to 1.5 V, VO = 0.5 V or 3 V ±50 ±50 µA TDO VCC = 1.5 V to 0, VO = 0.5 V or 3 V ±50 ±50 µA

I(hold)

VCC = 2.7 V, II = –18 mA –1.2 –1.2 V

VCC = 2.7 V, IOH = –3 mA 2.4 2.4

IOH = –8 mA 2.4 2.4

VCC = 3 V

VCC = 2.7 V, IOL = 24 mA 0.5 0.5

= 3

VCC = 3.6 V, VI = VCC or GND ±1 ±1 VCC = 0 or 3.6 V, VI = 5.5 V 10 10

VCC = 3.6 V

VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

= 3

= 3.6 V, IO = 0, VI = VCC or GND

VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND

VI = 3 V or 0 4 4 pF VO = 3 V or 0 10 10 pF VO = 3 V or 0 8 8 pF

includes the off-state output leakage current.

IOH = –24 mA 2 IOH = –32 mA 2

IOL = 16 mA 0.4 0.4 IOL = 32 mA 0.5 0.5 IOL = 48 mA 0.55 IOL = 64 mA 0.55

VI = 5.5 V 5 5 VI = V

VI = 0 –25 –100 –25 –100 VI = 5.5 V 20 20 VI = V

VI = 0 –5 –5

VI = 0.8 V 75 500 75 150 500 VI = 2 V –75 –500 –75 –150 –500

Outputs high 0.6 2 0.6 2 Outputs low 18 24 18 24 Outputs disabled 0.6 2 0.6 2

1 1

0.5 0.5 mA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

twPulse duration

A before LEAB↓ or

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

timing requirements over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14)

SN54LVTH182502A SN74LVTH182502A

clock

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAX

Clock frequency CLKAB or CLKBA 0 100 0 80 0 100 0 80 MHz

CLKAB or CLKBA high or low 4.4 5.6 4.4 5.6 LEAB or LEBA high 3 3 3 3

Setup time

Hold time

A before CLKAB↑ or B before CLKBA↑

A before LEAB↓ or B before LEBA↓

A after CLKAB↑ or B after CLKBA↑

A after LEAB↓ or B after LEBA↓ 3.1 3.5 3.1 3.5

CLK high 1.5 0.7 1.5 0.7 CLK low 1.6 1.6 1.6 1.6

2.8 3 2.8 3

1.4 1.1 1.4 1.1

VCC = 2.7 V

timing requirements over recommended operating free-air temperature range (unless otherwise noted) (test mode) (see Figure 14)

SN54LVTH182502A SN74LVTH182502A

clock

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAX

Clock frequency TCK 0 50 0 40 0 50 0 40 MHz Pulse duration TCK high or low 9.5 10.5 9.5 10.5 ns

A, B, CLK, LE, or OE

Setup time

Hold time

Delay time Power up to TCK↑ 50 50 50 50 ns Rise time VCC power up 1 1 1 1 µs

before TCK↑ TDI before TCK↑ TMS before TCK↑ 2.5 3.5 2.5 3.5 A, B, CLK, LE, or

after TCK↑ TDI after TCK↑ TMS after TCK↑ 1.5 1 1.5 1

6.5 7 6.5 7

2.5 3.5 2.5 3.5

1.5 1 1.5 1

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLKAB

CLKBA

LEAB

LEBA

OEAB

OEBA

B or A

OEAB or OEBA

B or A

TCK↓

A or B

TCK↓

TDO

TCK↓

A or B

TCK↓

TDO

TCK↓

A or B

TCK↓

TDO

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14)

SN54LVTH182502A SN74LVTH182502A

PARAMETER

max

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

FROM

(INPUT)

CLKAB or CLKBA 100 80 100 80 MHz

(OUTPUT)

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 6 6.7 1.5 5.7 6.4

1.5 5.1 5.8 1.5 4.9 5.6

1.5 7.1 8.1 1.5 6.7 7.7

1.5 6.3 7.2 1.5 5.8 6.8

1.5 8.7 9.7 1.5 8.2 9.2

1.5 6.5 6.9 1.5 6.2 6.7

1.5 7.8 9.2 1.5 7.4 8.4

1.5 6 6.6 1.5 5.7 6.4

1.5 8.4 9.6 1.5 7.9 8.7

2.5 9.1 9.3 2.5 8.4 8.9

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (test mode) (see Figure 14)

SN54LVTH182502A SN74LVTH182502A

PARAMETER

max

PLH

PHL

PLH

PHL

PZH

PZL

PZH

PZL

PHZ

PLZ

PHZ

PLZ

FROM

(INPUT)

TCK 50 40 50 40 MHz

(OUTPUT)

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAX

2.5 15 18 2.5 14 17

2.5 15 18 2.5 14 17 1 6 7 1 5.5 6.5

1.5 7 8 1.5 6.5 7.5 4 18 21 4 17 20 4 18 21 4 17 20 1 6 7 1 5.5 6.5

1.5 6 7 1.5 5.5 6.5 4 19 21 4 18 20 4 18 19.5 4 17 18.5

1.5 7.5 9 1.5 7 8.5

1.5 7.5 8.5 1.5 7 8

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668B – JULY 1996 – REVISED MARCH 1999

PARAMETER MEASUREMENT INFORMATION

6 V

From Output

Under Test

CL = 50 pF

(see Note A)

Input

500 Ω

LOAD CIRCUIT

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

Open

GND

2.7 V

0 V

Timing Input

Data Input

TEST S1

PLH/tPHL

PLZ/tPZL

PHZ/tPZH

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Open

GND

1.5 V

6 V

2.7 V

0 V

2.7 V

0 V

Input

PLH

Output

PHL

Output

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.

1.5 V 1.5 V

1.5 V

VOLTAGE WAVEFORMS

Figure 14. Load Circuit and Voltage Waveforms

PHL

1.5 V

PLH

1.5 V1.5 V

2.7 V

0 V

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

1.5 V1.5 V

PZL

1.5 V

PZH

1.5 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

VOL + 0.3 V

VOH – 0.3 V

PLZ

PHZ

2.7 V

0 V

3 V

[

0 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Datasheet SN74LVTH18502APM, SN74LVTH18502APMR, SN74LVTH182502APM, SNJ54LVTH18502AHV Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual