Datasheet SN74LVTH16835DGGR, SN74LVTH16835DL, SN74LVTH16835DLR Datasheet (Texas Instruments)
SN54LVTH16835, SN74LVTH16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERS
WITH 3-STATE OUTPUTS
SCBS713C – MARCH 1998 – REVISED APRIL 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
CC
)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
T ypical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, TA = 25°C
D
I
off
and Power-Up 3-State Support Hot
Insertion
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’L VTH16835 devices are 18-bit universal bus drivers designed for low-voltage (3.3-V) VCC operation, but
with the capability to provide a TTL interface to a 5-V system environment.
Data flow from A to Y is controlled by the output-enable (OE
) input. These devices operate in the transparent
mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high
or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of the clock.
When OE
is high, the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V
CC
is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE
should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Widebus is a trademark of Texas Instruments Incorporated.
SN54LVTH16835. . . WD PACKAGE
SN74LVTH16835... DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
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53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
Y1
GND
Y2
Y3
V
CC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y1 1
Y12
GND
Y13
Y14
Y15
V
CC
Y16
Y17
GND
Y18
OE
LE
GND
NC
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A1 1
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
CLK
GND
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LVTH16835, SN74LVTH16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERS
WITH 3-STATE OUTPUTS
SCBS713C – MARCH 1998 – REVISED APRIL 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54L VTH16835 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH16835 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT
OE LE CLK A
Y
H X X X Z
L HXL L
LHXH H
LL↑LL
LL↑HH
LLHX Y
0
†
LLLX Y
0
‡
†
Output level before the indicated steady-state
input conditions were established, provided
that CLK is high before LE goes low
‡
Output level before the indicated steady-state
input conditions were established
SN54LVTH16835, SN74LVTH16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERS
WITH 3-STATE OUTPUTS
SCBS713C – MARCH 1998 – REVISED APRIL 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
A6
47
A7
45
A8
44
A9
43
A10
42
A11
41
A12
40
A13
38
A14
37
A15
36
A16
34
A17
33
A18
31
OE
EN1
27
30
CLK
5
Y2
6
Y3
9
Y5
10
Y6
12
Y7
13
Y8
14
Y9
15
Y10
16
Y11
17
Y12
19
Y13
20
Y14
21
Y15
23
Y16
24
Y17
26
Y18
C3
28
LE
G2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2C3
8
Y4
1
1
3
Y1 A1
54
3D
A2
52
A3
51
A4
49
A5
48
logic diagram (positive logic)
OE
CLK
Y1
1D
C1
CLK
To 17 Other Channels
LE
A1
27
30
28
54
3
SN54LVTH16835, SN74LVTH16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERS
WITH 3-STATE OUTPUTS
SCBS713C – MARCH 1998 – REVISED APRIL 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, V
O
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54LVTH16835 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVTH16835 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
O
(see Note 2): SN54LVTH16835 48 mA. . . . . . . . . . . . . . . . . . . . .
SN74LVTH16835 64 mA. . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH16835 SN74LVTH16835
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 2.7 3.6 2.7 3.6 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 5.5 5.5 V
I
OH
High-level output current –24 –32 mA
I
OL
Low-level output current 48 64 mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
CC
Power-up ramp rate 200 200 µs/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVTH16835, SN74LVTH16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERS
WITH 3-STATE OUTPUTS
SCBS713C – MARCH 1998 – REVISED APRIL 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH16835 SN74LVTH16835
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4
V
OH
IOH = –24 mA 2
V
V
CC
=
3 V
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
V
CC
= 2.7
V
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
V
OL
IOL = 32 mA 0.5 0.5
V
V
CC
= 3
V
IOL = 48 mA 0.55
IOL = 64 mA 0.55
p
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
Control inputs
VCC = 3.6 V, VI = VCC or GND ±1 ±1
I
I
VI = V
CC
1 1
µA
A inputs
VCC = 3.6 V
VI = 5.5 V 10 10
VI = 0 –5 –5
I
off
VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
VI = 0.8 V 75 75
I
I(hold)
A inputs
V
CC
= 3
V
VI = 2 V –75 –75
µA
()
VCC = 3.6 V‡, VI = 0 to 3.6 V ±500
I
OZH
VCC = 3.6 V, VO = 3 V 5 5 µA
I
OZL
VCC = 3.6 V, VO = 0.5 V –5 –5 µA
I
OZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE
= don’t care
±100
∗
±100 µA
I
OZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE
= don’t care
±100
∗
±100 µA
=
Outputs high 0.19 0.19
I
CC
V
CC
= 3.6 V,
IO = 0,
Outputs low 5 5
mA
VI = VCC or GND
Outputs disabled 0.19 0.19
∆I
CC
§
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
0.2 0.2 mA
C
i
VI = 3 V or 0 3.5 3.5 pF
C
o
VO = 3 V or 0 9 9 pF
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVTH16835, SN74LVTH16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERS
WITH 3-STATE OUTPUTS
SCBS713C – MARCH 1998 – REVISED APRIL 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH16835 SN74LVTH16835
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
f
clock
Clock frequency 150 150 150 150 MHz
LE high 3.3 3.3 3.3 3.3
twPulse duration
CLK high or low 3.3 3.3 3.3 3.3
ns
Data before CLK↑ 2.2 2.5 2.1 2.4
t
su
Setup time
CLK high 2.5 1.7 2.3 1.5
ns
Data before LE↓
CLK low 1.5 0.5 1.5 0.5
Data after CLK↑ 1 0 1 0
thHold time
Data after LE↓ 0.8 0.8 0.8 0.8
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVTH16835 SN74LVTH16835
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
f
max
150 150 150 150 MHz
t
PLH
1.2 3.9 4.3 1.3 2.6 3.7 4
t
PHL
A
Y
1.2 3.9 4.3 1.3 2.4 3.7 4
ns
t
PLH
1.4 5.3 5.9 1.5 3.2 5.1 5.7
t
PHL
LE
Y
1.4 5.3 5.9 1.5 3.3 5.1 5.7
ns
t
PLH
1.4 5.3 5.9 1.5 3.5 5.1 5.7
t
PHL
CLK
Y
1.4 5.3 5.9 1.5 3.4 5.1 5.7
ns
t
PZH
1.2 5 5.9 1.3 2.9 4.6 5.5
t
PZL
OE
Y
1.2 5 5.9 1.3 3 4.6 5.5
ns
t
PHZ
1.6 6 6.5 1.7 4.2 5.8 6.3
t
PLZ
OE
Y
1.6 6 6.5 1.7 3.7 5.8 6.3
ns
†
All typical values are at VCC = 3.3 V, TA = 25°C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVTH16835, SN74LVTH16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERS
WITH 3-STATE OUTPUTS
SCBS713C – MARCH 1998 – REVISED APRIL 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500 Ω
500 Ω
Data Input
Timing Input
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
2.7 V
0 V
Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
3 V
0 V
VOL + 0.3 V
VOH – 0.3 V
≈ 0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
6 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
t
h
t
su
1.5 V 1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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BE FULLY AT THE CUSTOMER’S RISK.
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Copyright 1999, Texas Instruments Incorporated
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