SN54LVTH16652, SN74LVTH16652
3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS150K – JULY 1994 – REVISED APRIL 1999
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art Advanced BiCMOS
Family
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
D
Support Unregulated Battery Operation
CC
)
Down to 2.7 V
D
Typical V
< 0.8 V at V
D
I
off
and Power-Up 3-State Support Hot
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
Insertion
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
SN54LVTH16652.. . WD PACKAGE
SN74LVTH16652.. . DGG OR DL PACKAGE
1OEAB
1CLKAB
1SAB
2SAB
2CLKAB
2OEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1CLKBA
1SBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2SBA
2CLKBA
2OEBA
description
The ’L VTH16652 devices are 16-bit bus transceivers designed for low-voltage (3.3-V) VCC operation, but with
the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit
transceivers or one 16-bit transceiver.
Output-enable (OEAB and OEBA
and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects
real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the
typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data.
Figure 1 illustrates the four fundamental bus-management functions that can be performed with the
’LVTH16652 devices.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
) inputs are provided to control the transceiver functions. Select-control (SAB
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LVTH16652, SN74LVTH16652
OPERATION OR FUNCTION
3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS150K – JULY 1994 – REVISED APRIL 1999
description (continued)
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable
inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and OEBA
reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set
of bus lines remains at its last level configuration.
. In this configuration, each output
When V
However, to ensure the high-impedance state above 1.5 V, OE
is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.
CC
should be tied to VCC through a pullup resistor
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
These devices are fully specified for hot-insertion applications using I
and power-up 3-state. The I
off
circuitry
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54L VTH16652 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH16652 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OEAB
†
The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
‡
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
OEBA
L H H or L H or L X X Input Input Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ H or L X X Input Unspecified
H H ↑↑X
L X H or L ↑ X X Unspecified
L L ↑↑XX
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H H or L X H X Input Output Stored A data to B bus
H L H or L H or L H H Output Output
CLKAB CLKBA SAB SBA A1–A8 B1–B8
‡
X Input Output Store A in both registers
‡
DATA I/O
‡
Output Input Store B in both registers
†
‡
Input Hold A, store B
Store A, hold B
Stored A data to B bus and
stored B data to A bus
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16652, SN74LVTH16652
3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS150K – JULY 1994 – REVISED APRIL 1999
BUS A
OEAB
OEBA
LL
CLKABXCLKBAXSABXSBA
REAL-TIME TRANSFER
BUS B TO BUS A
BUS B
L
BUS A
OEABOEBA
HH
REAL-TIME TRANSFER
BUS B
CLKABXCLKBAXSABLSBA
X
BUS A TO BUS B
OEAB
X
L
L
BUS A
OEBA
CLKAB CLKBAXSABXSBA
H
X
H
STORAGE FROM
A, B, OR A AND B
BUS B
↑
XX
↑
↑↑
X
X
X
X
Figure 1. Bus-Management Functions
BUS A
OEAB OEBA
H L H or L H H
CLKAB CLKBA SAB SBA
H or L
TRANSFER STORED DA TA
TO A AND/OR B
BUS B
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LVTH16652, SN74LVTH16652
3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS150K – JULY 1994 – REVISED APRIL 1999
logic symbol
†
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
2OEBA
2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
56
1
55
54
2
3
29
28
30
31
27
26
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
EN1 [BA]
EN2 [AB]
C3
G4
C5
G6
EN7 [BA]
EN8 [AB]
C9
G10
C11
G12
≥ 1
1
5D
16
≥ 1
7
11D
12
112
6
4
4
10
10
≥ 1
≥ 1
1
1
3D
2
9D
52
1B1
51
1B2
49
1B3
48
1B4
47
1B5
45
1B6
44
1B7
43
1B8
42
2B1
8
41
2B2
40
2B3
38
2B4
37
2B5
36
2B6
34
2B7
33
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN54LVTH16652, SN74LVTH16652
3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS150K – JULY 1994 – REVISED APRIL 1999
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
1A1
2OEBA
56
1
55
54
2
3
5
29
One of Eight Channels
1D
C1
To Seven Other Channels
C1
1D
52
1B1
2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
2A1
28
30
31
27
26
15
One of Eight Channels
1D
C1
To Seven Other Channels
C1
1D
42
2B1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LVTH16652, SN74LVTH16652
UNIT
3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS150K – JULY 1994 – REVISED APRIL 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
†
Voltage range applied to any output in the high-impedance
or power-off state, V
Voltage range applied to any output in the high state, V
Current into any output in the low state, I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
: SN54LVTH16652 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .
O
SN74LVTH16652 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
(see Note 2): SN54LVTH16652 48 mA. . . . . . . . . . . . . . . . . . . . .
O
SN74LVTH16652 64 mA. . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
SN54LVTH16652 SN74LVTH16652
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
3 V
V
V
V
V
V
V
Control inputs
‡
V
V
()
V
CC
SN54LVTH16652, SN74LVTH16652
3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS150K – JULY 1994 – REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH16652 SN74LVTH16652
MIN TYP†MAX MIN TYP†MAX
V
IK
OH
OL
I
I
A or B ports
I
off
I
I(hold)
I
OZPU
I
OZPD
I
CC
∆I
CC
C
i
C
io
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
Unused pins at VCC or GND
§
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
A or B ports
¶
VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4
=
CC
= 2.7
CC
= 3
CC
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
p
VCC = 3.6 V, VI = VCC or GND ±1 ±1
VCC = 3.6 V
VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
= 3
CC
VCC = 3.6 V§, VI = 0 to 3.6 V ±500
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE
/OE = don’t care
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE
/OE = don’t care
=
= 3.6 V,
IO = 0,
VI = VCC or GND
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = 3 V or 0 4 4 pF
VO = 3 V or 0 10 10 pF
IOH = –24 mA 2
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
IOL = 32 mA 0.5 0.5
IOL = 48 mA 0.55
IOL = 64 mA 0.55
VI = 5.5 V 20 20
VI = V
CC
VI = 0 –5 –5
VI = 0.8 V 75 75
VI = 2 V –75 –75
Outputs high 0.19 0.19
Outputs low 5 5
Outputs disabled 0.19 0.19
1 1
±100* ±100 µA
±100* ±100 µA
0.2 0.2 mA
µA
µA
mA
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54LVTH16652, SN74LVTH16652
t
,
ns
t
h
ns
CLK
B or A
ns
A or B
B or A
ns
SAB or SBA
B or A
ns
OEBA
A
ns
OEBA
A
ns
OEAB
B
ns
OEAB
B
ns
3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS150K – JULY 1994 – REVISED APRIL 1999
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
SN54LVTH16652 SN74LVTH16652
f
clock
t
w
su
VCC = 3.3 V
± 0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
Clock frequency 150 150 150 150 MHz
Pulse duration, CLK high or low 3.3 3.3 3.3 3.3 ns
Setup time,
A or B before CLKAB↑ or CLKBA↑
Hold time,
A or B after CLKAB↑ or CLKBA↑
Data high 1.2 1.5 1.2 1.5
Data low
Data high 0.5 0 0.5 0
Data low 0.5 0.5 0.5 0.5
2 2.8 2 2.8
VCC = 2.7 V
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 2)
SN54LVTH16652 SN74LVTH16652
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
†
All typical values are at VCC = 3.3 V, TA = 25°C.
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
150 150 150 150 MHz
1.3 4.5 5 1.3 2.7 4.2 4.7
1.3 4.5 5 1.3 2.8 4.2 4.7
1 3.6 4.1 1 2.4 3.4 3.9
1 3.6 4.1 1 2.1 3.4 3.9
1 4.7 5.6 1 2.7 4.5 5.4
1 4.7 5.6 1 3 4.5 5.4
1 4.5 5.4 1 2.4 4.3 5.2
1 4.5 5.4 1 2.3 4.3 5.2
2 5.8 6.3 2 3.9 5.6 6.1
2 5.6 6.3 2 3.4 5.4 6.1
1.3 4.4 5.1 1.3 2.7 4.2 4.9
1.3 4.4 5.1 1.3 2.6 4.2 4.9
1.6 5.8 6.5 1.3 3.5 5.5 6.2
1.6 5.8 6.5 1.3 3.2 5.5 6.2
VCC = 2.7 V
VCC = 3.3
± 0.3 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
VCC = 2.7 V
UNIT
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16652, SN74LVTH16652
3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS150K – JULY 1994 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
500 Ω
500 Ω
t
w
1.5 V 1.5 V
1.5 V 1.5 V
S1
t
PHL
t
PLH
6 V
Open
GND
2.7 V
0 V
2.7 V
0 V
V
OH
V
OL
V
OH
V
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
1.5 V
1.5 V
Open
6 V
GND
1.5 V
t
h
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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BE FULLY AT THE CUSTOMER’S RISK.
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1999, Texas Instruments Incorporated
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