Texas Instruments SN74LVTH16652DGGR, SN74LVTH16652DL, SN74LVTH16652DLR Datasheet

SN54LVTH16652, SN74LVTH16652

3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS150K – JULY 1994 – REVISED APRIL 1999

D

Members of the Texas Instruments

Widebus

D

State-of-the-Art Advanced BiCMOS

 Family

Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation

D

Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With

3.3-V V

D

Support Unregulated Battery Operation

CC

)

Down to 2.7 V

D

Typical V
< 0.8 V at V

D

I

off

and Power-Up 3-State Support Hot

(Output Ground Bounce)

OLP

= 3.3 V, TA = 25°C

CC

Insertion

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

Latch-Up Performance Exceeds 500 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

SN54LVTH16652.. . WD PACKAGE

SN74LVTH16652.. . DGG OR DL PACKAGE

1OEAB

1CLKAB

1SAB

2SAB

2CLKAB

2OEAB

GND

1A1
1A2

V

CC

1A3
1A4
1A5

GND

1A6
1A7
1A8
2A1
2A2
2A3

GND

2A4
2A5
2A6

V

CC

2A7
2A8

GND

(TOP VIEW)

1

56

2

55

3

54

4

53

5

52

6

51

7

50

8

49

9

48

10

47

11

46

12

45

13

44

14

43

15

42

16

41

17

40

18

39

19

38

20

37

21

36

22

35

23

34

24

33

25

32

26

31

27

30

28

29

1OEBA
1CLKBA
1SBA
GND
1B1
1B2
V

CC

1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V

CC

2B7
2B8
GND
2SBA
2CLKBA
2OEBA

description

The ’L VTH16652 devices are 16-bit bus transceivers designed for low-voltage (3.3-V) VCC operation, but with
the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit
transceivers or one 16-bit transceiver.

Output-enable (OEAB and OEBA
and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects
real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the
typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data.
Figure 1 illustrates the four fundamental bus-management functions that can be performed with the
’LVTH16652 devices.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

) inputs are provided to control the transceiver functions. Select-control (SAB

Copyright  1999, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54LVTH16652, SN74LVTH16652

OPERATION OR FUNCTION

3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS150K – JULY 1994 – REVISED APRIL 1999

description (continued)

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable
inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and OEBA
reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set
of bus lines remains at its last level configuration.

. In this configuration, each output

When V
However, to ensure the high-impedance state above 1.5 V, OE

is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.

CC

should be tied to VCC through a pullup resistor
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
These devices are fully specified for hot-insertion applications using I

and power-up 3-state. The I

off

circuitry

off

disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.

The SN54L VTH16652 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH16652 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OEAB

†

The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

‡

Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.

OEBA

L H H or L H or L X X Input Input Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ H or L X X Input Unspecified

H H ↑↑X

L X H or L ↑ X X Unspecified
L L ↑↑XX
L L X X X L Output Input Real-time B data to A bus

L L X H or L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H H or L X H X Input Output Stored A data to B bus

H L H or L H or L H H Output Output

CLKAB CLKBA SAB SBA A1–A8 B1–B8

‡

X Input Output Store A in both registers

‡

DATA I/O

‡

Output Input Store B in both registers

†

‡

Input Hold A, store B

Store A, hold B

Stored A data to B bus and

stored B data to A bus

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH16652, SN74LVTH16652

3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS150K – JULY 1994 – REVISED APRIL 1999

BUS A

OEAB

OEBA

LL

CLKABXCLKBAXSABXSBA

REAL-TIME TRANSFER

BUS B TO BUS A

BUS B

L

BUS A

OEABOEBA

HH

REAL-TIME TRANSFER

BUS B

CLKABXCLKBAXSABLSBA

X

BUS A TO BUS B

OEAB

X
L
L

BUS A

OEBA

CLKAB CLKBAXSABXSBA

H
X
H

STORAGE FROM

A, B, OR A AND B

BUS B

↑

XX

↑
↑↑

X

X
X
X

Figure 1. Bus-Management Functions

BUS A

OEAB OEBA

H L H or L H H

CLKAB CLKBA SAB SBA

H or L

TRANSFER STORED DA TA

TO A AND/OR B

BUS B

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3