Texas Instruments SN74LVTH16543DGGR, SN74LVTH16543DL, SN74LVTH16543DLR Datasheet
SN54LVTH16543, SN74LVTH16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS699D – JULY 1997 – REVISED APRIL 1999
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art Advanced BiCMOS
Family
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
D
Support Unregulated Battery Operation
Down to 2.7 V
D
I
and Power-Up 3-State Support Hot
off
Insertion
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Typical V
< 0.8 V at V
D
Distributed VCC and GND Pin Configuration
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
CC
SN54LVTH16543.. . WD PACKAGE
SN74LVTH16543... DGG OR DL PACKAGE
1OEAB
1LEAB
1CEAB
)
2CEAB
2LEAB
2OEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
description
The ’L VTH16543 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) VCC operation, but
with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two
8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB
or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB
LEAB
is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB
) input must be low to enter data from A or to output data from B. If CEAB is low and
and OEAB both low, the 3-state B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to A is similar but requires using the CEBA
inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
or LEBA) and output-enable (OEAB
, LEBA, and OEBA
Copyright 1999, Texas Instruments Incorporated
1
SN54LVTH16543, SN74LVTH16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS699D – JULY 1997 – REVISED APRIL 1999
description (continued)
When VCC is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE
the minimum value of the resistor is determined by the current-sinking capability of the driver.
should be tied to VCC through a pullup resistor;
These devices are fully specified for hot-insertion applications using I
and power-up 3-state. The I
off
circuitry
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54L VTH16543 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH16543 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
CEAB LEAB OEAB A
H X X X Z
X XHXZ
LHLXB
LLLLL
LLLHH
†
A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA
‡
Output level before the indicated steady-state
input conditions were established
†
OUTPUT
B
‡
0
, LEBA, and OEBA.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16543, SN74LVTH16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS699D – JULY 1997 – REVISED APRIL 1999
logic symbol
†
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
56
54
55
1
3
2
29
31
30
28
26
27
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
1EN3
G1
1C5
2EN4
G2
2C6
7EN9
G7
7C11
8EN10
G8
8C12
3
6D
9
12D
5D
4
11D
10
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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