Datasheet SN74LVTH16543DGGR, SN74LVTH16543DL, SN74LVTH16543DLR Datasheet (Texas Instruments)

SN54LVTH16543, SN74LVTH16543

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS699D – JULY 1997 – REVISED APRIL 1999

D

Members of the Texas Instruments

Widebus

D

State-of-the-Art Advanced BiCMOS

 Family

Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation

D

Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V

D

Support Unregulated Battery Operation
Down to 2.7 V

D

I

and Power-Up 3-State Support Hot

off

Insertion

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Typical V
< 0.8 V at V

D

Distributed VCC and GND Pin Configuration

(Output Ground Bounce)

OLP

= 3.3 V, TA = 25°C

CC

Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

Latch-Up Performance Exceeds 500 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

CC

SN54LVTH16543.. . WD PACKAGE

SN74LVTH16543... DGG OR DL PACKAGE

1OEAB

1LEAB

1CEAB

)

2CEAB

2LEAB

2OEAB

GND

1A1
1A2

V

CC

1A3
1A4
1A5

GND

1A6
1A7
1A8
2A1
2A2
2A3

GND

2A4
2A5
2A6

V

CC

2A7
2A8

GND

(TOP VIEW)

1

56

2

55

3

54

4

53

5

52

6

51

7

50

8

49

9

48

10

47

11

46

12

45

13

44

14

43

15

42

16

41

17

40

18

39

19

38

20

37

21

36

22

35

23

34

24

33

25

32

26

31

27

30

28

29

1OEBA
1LEBA
1CEBA
GND
1B1
1B2
V

CC

1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V

CC

2B7
2B8
GND
2CEBA
2LEBA
2OEBA

description

The ’L VTH16543 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) VCC operation, but
with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two
8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB
or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable (CEAB
LEAB

is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches

in the storage mode. With CEAB

) input must be low to enter data from A or to output data from B. If CEAB is low and

and OEAB both low, the 3-state B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to A is similar but requires using the CEBA
inputs.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

or LEBA) and output-enable (OEAB

, LEBA, and OEBA

Copyright  1999, Texas Instruments Incorporated

1

SN54LVTH16543, SN74LVTH16543

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS699D – JULY 1997 – REVISED APRIL 1999

description (continued)

When VCC is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE
the minimum value of the resistor is determined by the current-sinking capability of the driver.

should be tied to VCC through a pullup resistor;

These devices are fully specified for hot-insertion applications using I

and power-up 3-state. The I

off

circuitry

off

disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.

The SN54L VTH16543 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH16543 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each 8-bit section)

INPUTS

CEAB LEAB OEAB A

H X X X Z
X XHXZ

LHLXB
LLLLL
LLLHH

†

A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA

‡

Output level before the indicated steady-state
input conditions were established

†

OUTPUT

B

‡

0

, LEBA, and OEBA.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH16543, SN74LVTH16543

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS699D – JULY 1997 – REVISED APRIL 1999

logic symbol

†

1OEBA
1CEBA

1LEBA
1OEAB
1CEAB

1LEAB
2OEBA
2CEBA

2LEBA
2OEAB
2CEAB

2LEAB

1A1

1A2
1A3
1A4
1A5
1A6
1A7
1A8

2A1

2A2
2A3
2A4
2A5
2A6
2A7
2A8

56
54
55
1
3
2
29
31
30
28
26
27

5

6
8
9
10
12
13
14

15

16
17
19
20
21
23
24

1EN3
G1
1C5
2EN4
G2
2C6
7EN9
G7
7C11
8EN10
G8
8C12

3

6D

9

12D

5D
4

11D
10

52

51
49
48
47
45
44
43

42

41
40
38
37
36
34
33

1B1

1B2
1B3
1B4
1B5
1B6
1B7
1B8

2B1

2B2
2B3
2B4
2B5
2B6
2B7
2B8

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54LVTH16543, SN74LVTH16543

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS699D – JULY 1997 – REVISED APRIL 1999

logic diagram (positive logic)

1OEBA

1CEBA

1LEBA

1OEAB

1CEAB

1LEAB

1A1

2OEBA

56

54

55
1

3

2

5

29

C1
1D

To Seven Other Channels

C1
1D

52

1B1

2CEBA

2LEBA

2OEAB

2CEAB

2LEAB

2A1

31

30
28

26

27

15

C1
1D

To Seven Other Channels

C1
1D

42

2B1

4

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UNIT

SN54LVTH16543, SN74LVTH16543

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS699D – JULY 1997 – REVISED APRIL 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

†

Voltage range applied to any output in the high-impedance

or power-off state, V
Voltage range applied to any output in the high state, V
Current into any output in the low state, I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

: SN54LVTH16543 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .

O

SN74LVTH16543 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the high state, I

(see Note 2): SN54LVTH16543 48 mA. . . . . . . . . . . . . . . . . . . . .

O

SN74LVTH16543 64 mA. . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Output clamp current, I
Package thermal impedance, θ

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 4)

SN54LVTH16543 SN74LVTH16543

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V

T

A

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA

Power-up ramp rate 200 200 µs/V

CC

Operating free-air temperature –55 125 –40 85 °C

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54LVTH16543, SN74LVTH16543

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

V

V

V

V

V

V

V

Control inputs

‡

V

3 V

()

V

CC

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS699D – JULY 1997 – REVISED APRIL 1999

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LVTH16543 SN74LVTH16543

MIN TYP†MAX MIN TYP†MAX

V

IK

OH

OL

I

I

A or B ports

I

off

I

I(hold)

I

OZPU

I

OZPD

I

CC

∆I

CC

C

i

C

io

* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

Unused pins at VCC or GND

§

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

¶

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

A or B ports

¶

VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4

= 3

CC

= 2.7

CC

= 3

CC

VCC = 3.6 V, VI = VCC or GND ±1 ±1

p

VCC = 0 or 3.6 V, VI = 5.5 V 10 10

VCC = 3.6 V

VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

=

CC

VCC = 3.6 V§, VI = 0 to 3.6 V ±500
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,

OE

= don’t care

VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE

= don’t care

=

= 3.6 V,
IO = 0,
VI = VCC or GND

VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND

VI = 3 V or 0 4 4 pF
VO = 3 V or 0 10 10 pF

IOH = –24 mA 2
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
IOL = 32 mA 0.5 0.5
IOL = 48 mA 0.55
IOL = 64 mA 0.55

VI = 5.5 V 20 20
VI = V

CC

VI = 0 –5 –5

VI = 0.8 V 75 75
VI = 2 V –75 –75

Outputs high 0.19 0.19
Outputs low 5 5
Outputs disabled 0.19 0.19

1 1

±100* ±100 µA

±100* ±100 µA

0.2 0.2 mA

µA

µA

mA

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

A or B before

t

Set

ns

A or B before

A or B after

t

Hold time

ns

A or B

B or A

ns

LE

A or B

ns

OE

A or B

ns

OE

A or B

ns

CE

A or B

ns

CE

A or B

ns

SN54LVTH16543, SN74LVTH16543

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS699D – JULY 1997 – REVISED APRIL 1999

timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)

SN54LVTH16543 SN74LVTH16543

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAX

t

w

su

h

Pulse duration, LEAB or LEBA low 3.3 3.3 3.3 3.3 ns

A or B before
LEAB↑ or LEBA↑

up time

A or B before
CEAB↑ or CEBA↑

A or B after
LEAB↑ or LEBA↑

A or B after
CEAB↑ or CEBA↑

Data high 0.5 0.5 0.5 0.5
Data low 0.8 1.3 0.8 1.3
Data high 0 0 0 0
Data low 0.6 1.1 0.6 1.1
Data high 1.5 0.7 1.5 0.7
Data low 1.2 1.3 1.2 1.3
Data high 1.7 0.9 1.7 0.9
Data low 1.6 1.8 1.6 1.8

VCC = 2.7 V

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

SN54LVTH16543 SN74LVTH16543

PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

PZH

t

PZL

t

PHZ

t

PLZ

†

All typical values are at VCC = 3.3 V, TA = 25°C.

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN TYP†MAX MIN MAX

1.1 3.4 3.9 1.2 2.3 3.2 3.7

1.1 3.4 3.9 1.2 2.1 3.2 3.7

1.2 4.1 5.1 1.3 2.5 3.9 4.9

1.2 4.1 5.1 1.3 2.3 3.9 4.9

1.2 4.5 5.6 1.3 2.8 4.3 5.4

1.2 4.5 5.6 1.3 2.8 4.3 5.4

1.9 4.9 5.4 2 3.5 4.7 5.2

1.9 4.6 4.7 2 3.3 4.4 4.5

1.2 4.7 5.8 1.3 3 4.5 5.6

1.2 4.7 5.8 1.3 3 4.5 5.6

1.9 5.1 5.6 2 3.6 4.9 5.4

1.9 4.9 5.1 2 3.5 4.7 4.9

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 2.7 V

UNIT

UNIT

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

SN54LVTH16543, SN74LVTH16543

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS699D – JULY 1997 – REVISED APRIL 1999

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

500 Ω

500 Ω

LOAD CIRCUIT

t

w

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

1.5 V 1.5 V

t

PHL

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

S1

t

PHL

t

PLH

6 V

Open

GND

2.7 V

0 V

V

V

V

V

2.7 V

0 V

OH

OL

OH

OL

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

t

PZL

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

1.5 V

1.5 V

Open

6 V

GND

1.5 V

t

h

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

2.7 V

0 V

2.7 V

0 V

2.7 V

0 V

3 V

V

OL

V

OH

≈ 0 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

8

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Copyright  1999, Texas Instruments Incorporated