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SN74LVTH16541DGGR

Datasheet SN74LVTH16541DLR, SN74LVTH16541DGGR, SN74LVTH16541DL Datasheet (Texas Instruments)

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SN54LVTH16541, SN74LVTH16541
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS691D – MAY 1997 – REVISED APRIL 1999
D
Widebus
D
State-of-the-Art Advanced BiCMOS
Family
Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
D
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With
3.3-V V
D
Support Unregulated Battery Operation
CC
)
Down to 2.7 V
D
Typical V < 0.8 V at V
D
I
off
and Power-Up 3-State Support Hot
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
Insertion
D
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
D
Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB Layout
D
Latch-Up Performance Exceeds 500 mA Per JESD 17
D
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54LVTH16541. . . WD PACKAGE
SN74LVTH16541. . . DGG OR DL PACKAGE
1OE1
1Y1 1Y2
GND
1Y3 1Y4
V
CC
1Y5 1Y6
GND
1Y7 1Y8 2Y1 2Y2
GND
2Y3 2Y4
V
CC
2Y5 2Y6
GND
2Y7 2Y8
2OE1
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE2 1A1 1A2 GND 1A3 1A4 V
CC
1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 V
CC
2A5 2A6 GND 2A7 2A8 2OE2
description
These 16-bit buffers/drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
These devices are noninverting 16-bit buffers composed of two 8-bit sections with separate output-enable signals. For either 8-bit buffer section, the two output-enable (1OE1 be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 8-bit buffer section are in the high-impedance state.
When V
is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
and 1OE2 or 2OE1 and 2OE2) inputs must
should be tied to VCC through a pullup resistor;
Copyright 1999, Texas Instruments Incorporated
1
SN54LVTH16541, SN74LVTH16541
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS691D – MAY 1997 – REVISED APRIL 1999
description (continued)
These devices are fully specified for hot-insertion applications using I
and power-up 3-state. The I
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
The SN54L VTH16541 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVTH16541 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
logic symbol
INPUTS
OE2 A
OE1
L L L L
L LH H HXX Z XHX Z
†
1OE1 1OE2
2OE1 2OE2
1 48
24 25
&
&
OUTPUT
Y
EN1
EN2
circuitry
off
47
1A1
46
1A2
44
1A3
43
1A4
41
1A5
40
1A6
38
1A7
37
1A8
36
2A1
35
2A2
33
2A3
32
2A4
30
2A5
29
2A6
27
2A7
26
2A8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
111
2
11 12 13 14 16 17 19 20 22 23
2
1Y1
3
1Y2
5
1Y3
6
1Y4
8
1Y5
9
1Y6 1Y7 1Y8 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
logic diagram (positive logic)
SN54LVTH16541, SN74LVTH16541
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS691D – MAY 1997 – REVISED APRIL 1999
1
1OE1
48
1OE2
47
1A1 1Y1
To Seven Other Channels To Seven Other Channels
2
2OE1 2OE2
2A1
24 25
36
13
2Y1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V Input voltage range, V Voltage range applied to any output in the high-impedance or power-off state, V Voltage range applied to any output in the high state, V Current into any output in the low state, I
Current into any output in the high state, I Input clamp current, I
Output clamp current, I Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
: SN54LVTH16541 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .
O
SN74LVTH16541 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): SN54LVTH16541 48 mA. . . . . . . . . . . . . . . . . . . . .
O
SN74LVTH16541 64 mA. . . . . . . . . . . . . . . . . . . . .
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
recommended operating conditions (see Note 4)
SN54LVTH16541 SN74LVTH16541
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V ∆t/∆V
T
A
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Supply voltage 2.7 3.6 2.7 3.6 V High-level input voltage 2 2 V Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.5 V High-level output current –24 –32 mA Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LVTH16541, SN74LVTH16541
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
V
V
V
V
V
V
I
A
D
V
3.6 V
V
V
I
I(hold)
Data in uts
µA
V
CC
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS691D – MAY 1997 – REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LVTH16541 SN74LVTH16541
MIN TYP†MAX MIN TYP†MAX
V
IK
OH
OL
I
I
off
I
OZH
I
OZL
I
OZPU
I
OZPD
I
CC
∆I
CC
C
i
C
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested. †
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Control inputs VCC = 3.6 V, VI = VCC or GND ±1 ±1
ata inputs
p
§
VCC = 2.7 V, II = –18 mA –1.2 –1.2 V VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2 VCC = 2.7 V, IOH = –8 mA 2.4 2.4
= 3
CC
= 2.7
CC
= 3
CC
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
=
CC
VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
= 3
CC
VCC = 3.6 V‡, VI = 0 to 3.6 V VCC = 3.6 V, VO = 3 V 5 5 µA
VCC = 3.6 V, VO = 0.5 V –5 –5 µA VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE
= don’t care
VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE
= don’t care
=
= 3.6 V, IO = 0, VI = VCC or GND
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND
VI = 3 V or 0 4 4 pF VO = 3 V or 0 9 9 pF
IOH = –24 mA 2 IOH = –32 mA 2 IOL = 100 µA 0.2 0.2 IOL = 24 mA 0.5 0.5 IOL = 16 mA 0.4 0.4 IOL = 32 mA 0.5 0.5 IOL = 48 mA 0.55 IOL = 64 mA 0.55
VI = V
CC
VI = 0 –5 –5
VI = 0.8 V 75 75 VI = 2 V –75 –75
Outputs high 0.19 0.19 Outputs low 5 5 Outputs disabled 0.19 0.19
1 1
500
–750
±100* ±100 µA
±100* ±100 µA
0.2 0.2 mA
µ
mA
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
A
Y
ns
OE
Y
ns
OE
Y
ns
SN54LVTH16541, SN74LVTH16541
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS691D – MAY 1997 – REVISED APRIL 1999
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVTH16541 SN74LVTH16541
PARAMETER
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
†
All typical values are at VCC = 3.3 V, TA = 25°C.
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
1 3.7 4 1 2.4 3.5 3.8 1 3.7 4 1 2 3.5 3.8
1.1 4.8 5.7 1.2 2.7 4.6 5.5
1.1 4.8 5.4 1.2 2.8 4.6 5.2
2.1 6.2 6.5 2.2 4.1 5.9 6.2
1.9 5.7 6 2.2 3.8 5.4 5.5
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
0.5 0.5 ns
UNIT
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LVTH16541, SN74LVTH16541
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS691D – MAY 1997 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
500 Ω
S1
6 V
GND
Open
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
LOAD CIRCUIT
t
w
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
1.5 V 1.5 V
t
PHL
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
t
PHL
t
PLH
2.7 V
0 V
V
OH
V
OL
V
OH
V
OL
2.7 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
h
VOL + 0.3 V
VOH – 0.3 V
t
PLZ
t
PHZ
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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