Texas Instruments SN74LVTH16501DGGR, SN74LVTH16501DL, SN74LVTH16501DLR Datasheet
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700D – JULY 1997 – REVISED APRIL 1999
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art Advanced BiCMOS
Family
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
D
Support Unregulated Battery Operation
Down to 2.7 V
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D
Typical V
< 0.8 V at V
D
I
off
and Power-Up 3-State Support Hot
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
Insertion
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
CC
SN54LVTH16501.. . WD PACKAGE
SN74LVTH16501... DGG OR DL PACKAGE
OEAB
LEAB
)
OEBA
LEBA
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A1 1
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B1 1
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
GND
description
The ’L VTH16501 devices are 18-bit universal bus transceivers designed for low-voltage (3.3-V) VCC operation,
but with the capability to provide a TTL interface to a 5-V system environment.
Data flow in each direction is controlled by output-enable (OEAB and OEBA
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when
LEAB is high. When LEAB is low , the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the
outputs are active. When OEAB is low, the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and UBT are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
), latch-enable (LEAB and LEBA),
Copyright 1999, Texas Instruments Incorporated
1
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700D – JULY 1997 – REVISED APRIL 1999
description (continued)
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
is active low).
When V
However, to ensure the high-impedance state above 1.5 V, OE
is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.
CC
should be tied to VCC through a pullup resistor
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
These devices are fully specified for hot-insertion applications using I
and power-up 3-state. The I
off
circuitry
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54L VTH16501 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH16501 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OEAB LEAB CLKAB A
L X X X Z
H HX LL
HHX HH
HL= LL
HL↑ HH
H LH XB
HLL XB
†
A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA
‡
Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was high before LEAB went low
§
Output level before the indicated steady-state input
conditions were established
, LEBA, and CLKBA.
†
OUTPUT
B
‡
0
§
0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700D – JULY 1997 – REVISED APRIL 1999
logic symbol
†
OEAB
CLKAB
LEAB
OEBA
CLKBA
LEBA
1
55
2
27
30
28
3
A1 B1
5
A2
6
A3
8
A4
9
A5
10
A6
12
A7
13
A8
14
A9
15
A10
16
A11
17
A12
19
A13
20
A14
21
A15
23
A16
24
A17
26
A18
EN1
C3
G2
EN4
C6
G5
3D
4
2C3
5C6
11
1
6D
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
Loading...