Texas Instruments SN74LVTH16373DGGR, SN74LVTH16373DL, SN74LVTH16373DLR, SNJ54LVTH16373WD Datasheet

SN54LVTH16373, SN74LVTH16373

3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS144K – MAY 1992 – REVISED APRIL 1999

D

Members of the Texas Instruments

Widebus

D

State-of-the-Art Advanced BiCMOS

 Family

Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation

D

Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With

3.3-V V

D

Support Unregulated Battery Operation

CC

)

Down to 2.7 V

D

Typical V
< 0.8 V at V

D

I

off

and Power-Up 3-State Support Hot

(Output Ground Bounce)

OLP

= 3.3 V, TA = 25°C

CC

Insertion

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

Latch-Up Performance Exceeds 500 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

SN54LVTH16373. . . WD PACKAGE

SN74LVTH16373... DGG OR DL PACKAGE

1OE

1Q1
1Q2

GND

1Q3
1Q4

V

CC

1Q5
1Q6

GND

1Q7
1Q8
2Q1
2Q2

GND

2Q3
2Q4

V

CC

2Q5
2Q6

GND

2Q7
2Q8

2OE

(TOP VIEW)

1

48

2

47

3

46

4

45

5

44

6

43

7

42

8

41

9

40

10

39

11

38

12

37

13

36

14

35

15

34

16

33

17

32

18

31

19

30

20

29

21

28

22

27

23

26

24

25

1LE
1D1
1D2
GND
1D3
1D4
V

CC

1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V

CC

2D5
2D6
GND
2D7
2D8
2LE

description

The ’LVTH16373 devices are 16-bit transparent D-type latches with 3-state outputs designed for low-voltage
(3.3-V) V
devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and
working registers.

These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up
at the D inputs.

Widebus is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

operation, but with the capability to provide a TTL interface to a 5-V system environment. These

CC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  1999, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54LVTH16373, SN74LVTH16373

3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS144K – MAY 1992 – REVISED APRIL 1999

description (continued)

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and the increased drive provide the capability to drive bus
lines without interface or pullup components.

OE

does not affect internal operations of the latch. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V

However, to ensure the high-impedance state above 1.5 V, OE

is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.

CC

should be tied to VCC through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I

and power-up 3-state. The I

off

circuitry

off

disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.

The SN54L VTH16373 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH16373 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each 8-bit section)

INPUTS

OE

LE D

L H H H
L HL L
LLX Q

HXX Z

OUTPUT

Q

0

2

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SN54LVTH16373, SN74LVTH16373

3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS144K – MAY 1992 – REVISED APRIL 1999

logic symbol

†

1LE

2LE

1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8

1
48
24
25

47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26

1EN
C3
2EN
C4

3D

4D

11
12
13
14
16
17
19
20
22
23

2

1Q1

3

1Q2

5

1Q3

6

1Q4

8

1Q5

9

1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8

1

2

1OE

2OE

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

1OE

1LE

1D1

1

48

47

C1
1D

To Seven Other Channels

1Q1

2OE

2LE

2D1

24

25

36

C1
1D

To Seven Other Channels

132

2Q1

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3

SN54LVTH16373, SN74LVTH16373

UNIT

3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS144K – MAY 1992 – REVISED APRIL 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

†

Voltage range applied to any output in the high-impedance

or power-off state, V
Voltage range applied to any output in the high state, V
Current into any output in the low state, I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

: SN54LVTH16373 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .

O

SN74LVTH16373 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the high state, I

(see Note 2): SN54LVTH16373 48 mA. . . . . . . . . . . . . . . . . . . . .

O

SN74LVTH16373 64 mA. . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Output clamp current, I
Package thermal impedance, θ

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 4)

SN54LVTH16373 SN74LVTH16373

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V

T

A

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA

Power-up ramp rate 200 200 µs/V

CC

Operating free-air temperature –55 125 –40 85 °C

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

4

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PARAMETER

TEST CONDITIONS

UNIT

V

V

V

V

V

V

V

V

V

V

I

A

D

V

3.6 V

V

V

I

I(hold)

Data in uts

µA

V

CC

SN54LVTH16373, SN74LVTH16373

3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS144K – MAY 1992 – REVISED APRIL 1999

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LVTH16373 SN74LVTH16373

MIN TYP†MAX MIN TYP†MAX

V

IK

OH

OL

I

I

off

I

OZH

I

OZL

I

OZPU

I

OZPD

I

CC

∆I

CC

C

i

C

o

* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

Control inputs VCC = 3.6 V, VI = VCC or GND ±1 ±1

ata inputs

p

§

VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4

= 3

CC

= 2.7

CC

= 3

CC

VCC = 0 or 3.6 V, VI = 5.5 V 10 10

=

CC

VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

= 3

CC

VCC = 3.6 V‡, VI = 0 to 3.6 V
VCC = 3.6 V, VO = 3 V 5 5 µA

VCC = 3.6 V, VO = 0.5 V –5 –5 µA
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,

OE

= don’t care

VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE

= don’t care

=

= 3.6 V,
IO = 0,
VI = VCC or GND

VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND

VI = 3 V or 0 3 3 pF
VO = 3 V or 0 9 9 pF

IOH = –24 mA 2
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
IOL = 32 mA 0.5 0.5
IOL = 48 mA 0.55
IOL = 64 mA 0.55

VI = V

CC

VI = 0 –5 –5

VI = 0.8 V 75 75
VI = 2 V –75 –75

Outputs high 0.19 0.19
Outputs low 5 5
Outputs disabled 0.19 0.19

1 1

500

–750

±100* ±100 µA

±100* ±100 µA

0.2 0.2 mA

µ

mA

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5

SN54LVTH16373, SN74LVTH16373

D

Q

ns

LE

Q

ns

OE

Q

ns

OE

Q

ns

3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS144K – MAY 1992 – REVISED APRIL 1999

timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)

SN54LVTH16373 SN74LVTH16373

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAX

t

w

t

su

t

h

Pulse duration, LE high 3 3 3 3 ns
Setup time, data before LE↓ 2 2 1 0.6 ns
Hold time, data after LE↓ 3 3.3 1 1.1 ns

VCC = 2.7 V

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

SN54LVTH16373 SN74LVTH16373

PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

sk(o)

†

All typical values are at VCC = 3.3 V, TA = 25°C.

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN TYP†MAX MIN MAX

1.4 4.5 5.2 1.5 2.7 3.8 4.2

1.4 4.4 4.8 1.5 2.5 3.6 4

1.8 5.5 5.8 2.1 3 4.3 4.8

1.8 5.2 5.6 2.1 2.9 4 4

1.4 5.7 6.7 1.5 2.8 4.3 5.1

1.4 5.5 6 1.5 2.8 4.3 4.7
2 6 6.2 2.4 3.5 5 5.4

1.4 5.2 5.6 2 3.2 4.7 4.8

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 2.7 V

0.5 ns

UNIT

UNIT

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVTH16373, SN74LVTH16373

3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS144K – MAY 1992 – REVISED APRIL 1999

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

500 Ω

500 Ω

LOAD CIRCUIT

t

w

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

1.5 V 1.5 V

t

PHL

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

S1

t

PHL

t

PLH

6 V

Open

GND

2.7 V

0 V

V

V

V

V

2.7 V

0 V

OH

OL

OH

OL

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

t

PZL

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

1.5 V

1.5 V

Open

6 V

GND

1.5 V

t

h

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

2.7 V

0 V

2.7 V

0 V

2.7 V

0 V

3 V

V

OL

V

OH

≈ 0 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

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7

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Copyright  1999, Texas Instruments Incorporated