Texas Instruments SN74LVTH16244ADGGR, SN74LVTH16244ADGVR, SN74LVTH16244ADL, SN74LVTH16244ADLR Datasheet
SN54LVTH16244A, SN74LVTH16244A
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS142L – MAY 1992 – REVISED APRIL 1999
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art Advanced BiCMOS
Family
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
I
and Power-Up 3-State Support Hot
off
Insertion
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
SN54LVTH16244A. .. WD PACKAGE
SN74LVTH16244A. .. DGG, DGV, OR DL PACKAGE
1OE
1Y1
1Y2
GND
1Y3
1Y4
V
CC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
V
CC
4Y1
4Y2
GND
4Y3
4Y4
4OE
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
V
CC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
V
CC
4A1
4A2
GND
4A3
4A4
3OE
description
The ’L VTH16244A devices are 16-bit buffers and line drivers designed for low-voltage (3.3-V) VCC operation,
but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as
four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical
active-low output-enable (OE) inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 1.5-V , the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5-V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
and power-up 3-state. The I
off
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
circuitry
off
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LVTH16244A, SN74LVTH16244A
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS142L – MAY 1992 – REVISED APRIL 1999
description (continued)
The SN54LVTH16244A is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74LVTH16244A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OE
L H H
L LL
H X Z
OUTPUT
A
Y
logic symbol
†
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
1
48
25
24
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
EN1
EN2
EN3
EN4
11
12
13
14
16
17
19
20
22
23
2
1Y1
3
1Y2
5
1Y3
6
1Y4
8
2Y1
9
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
1
1
1
2
1
3
1
4
1OE
2OE
3OE
4OE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN54LVTH16244A, SN74LVTH16244A
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS142L – MAY 1992 – REVISED APRIL 1999
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
47
46
44
43
48
41
40
38
37
11
12
25
3OE
2
1Y1
3
1Y2
5
1Y3
6
1Y4
8
2Y1
9
2Y2
2Y3
2Y4
3A1
3A2
3A3
3A4
4OE
4A1
4A2
4A3
4A4
36
35
33
32
24
30
29
27
26
13
14
16
17
19
20
22
23
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in
or power-off state, VO (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .
Current into any output in the low state, IO: SN54LVTH16244A 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
JA
stg
the high-impedance
SN74LVTH16244A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): SN54LVTH16244A 48 mA. . . . . . . . . . . . . . . . . . . .
O
SN74LVTH16244A 64 mA. . . . . . . . . . . . . . . . . . . .
(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LVTH16244A, SN74LVTH16244A
UNIT
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS142L – MAY 1992 – REVISED APRIL 1999
recommended operating conditions (see Note 4)
SN54LVTH16244A SN74LVTH16244A
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
V
2.7 V
V
V
V
V
I
A
D
V
V
V
V
I
I(hold)
Data in uts
µA
V
CC
SN54LVTH16244A, SN74LVTH16244A
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS142L – MAY 1992 – REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH16244A SN74LVTH16244A
MIN TYP†MAX MIN TYP†MAX
V
IK
OH
OL
I
I
off
I
OZH
I
OZL
I
OZPU
I
OZPD
I
CC
∆I
CC
C
i
C
o
*On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Control inputs VCC = 3.6 V, VI = VCC or GND ±1 ±1
ata inputs
p
§
VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4
= 3
CC
=
CC
= 3
CC
VCC = 0 or 3.6 V, VI = 5.5 V 50 10
= 3.6
CC
VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
= 3
CC
VCC = 3.6 V‡, VI = 0 to 3.6 V
VCC = 3.6 V, VO = 3 V 5 5 µA
VCC = 3.6 V, VO = 0.5 V –5 –5 µA
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE
= don’t care
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE
= don’t care
=
= 3.6 V,
IO = 0,
VI = VCC or GND
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = 3 V or 0 4 4 pF
VO = 3 V or 0 9 9 pF
IOH = –24 mA 2
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
IOL = 32 mA 0.5 0.5
IOL = 48 mA 0.55
IOL = 64 mA 0.55
VI = V
CC
VI = 0 –5 –5
VI = 0.8 V 75 75
VI = 2 V –75 –75
Outputs high 0.19 0.19
Outputs low 5 5
Outputs disabled 0.19 0.19
1 1
500
–750
±100* ±100 µA
±100* ±100 µA
0.2 0.2 mA
µ
mA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LVTH16244A, SN74LVTH16244A
A
Y
ns
OE
Y
ns
OE
Y
ns
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS142L – MAY 1992 – REVISED APRIL 1999
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVTH16244A SN74LVTH16244A
PARAMETER
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
†
All typical values are at VCC = 3.3 V, TA = 25°C.
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
1.1 4.4 4.6 1.2 2.3 3.2 3.7
1.1 3.6 3.9 1.2 2 3.2 3.7
1.1 4.6 5.4 1.2 2.6 4 5
1.1 5.4 6.2 1.2 2.7 4 5
1.6 5.7 6.2 2.2 3.3 4.5 5
1.2 5 4.7 2 3.1 4.2 4.4
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
0.5 ns
UNIT
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
SN54LVTH16244A, SN74LVTH16244A
3.3-V ABT 16-BIT BUFFERS/DRIVERS
SCBS142L – MAY 1992 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
6 V
500 Ω
500 Ω
S1
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
WITH 3-STATE OUTPUTS
Open
6 V
GND
LOAD CIRCUIT
t
w
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
1.5 V 1.5 V
t
PHL
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
PHL
t
PLH
2.7 V
0 V
V
OH
V
OL
V
OH
V
OL
2.7 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
h
VOL + 0.3 V
VOH – 0.3 V
t
t
PLZ
PHZ
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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7
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 2000, Texas Instruments Incorporated
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