Datasheet SN74LVTH125DGVR, SN74LVTH125DR, SN74LVTH125PWR, SN74LVTH125D, SN74LVTH125DBR Datasheet (Texas Instruments)

SN54LVTH125, SN74LVTH125

3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS

SCBS703E – AUGUST 1997 – REVISED APRIL 1999

D

State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation

D

Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V

D

Support Unregulated Battery Operation
Down to 2.7 V

D

Typical V
< 0.8 V at V

D

I

off

and Power-Up 3-State Support Hot

(Output Ground Bounce)

OLP

= 3.3 V, TA = 25°C

CC

Insertion

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Latch-Up Performance Exceeds 500 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) DIPs

CC

SN54LVTH125...J PACKAGE

SN74LVTH125. . . D, DB, OR PW PACKAGE

)

SN54LVTH125. . . FK PACKAGE

1Y

NC

2OE

NC

2A

NC – No internal connection

(TOP VIEW)

1OE

1

1A

2

1Y

3

2OE

4

2A

5

2Y

6

GND

7

(TOP VIEW)

1A

3212019

4
5
6
7
8

910111213

2Y

1OE

GND

NC

NC

14
13
12

10

V

CC

4OE
4A
4Y

11

3OE
3A

9

3Y

8

CC

V

4OE

4A

18
17

NC

16

4Y

15

NC

14

3OE

3Y

3A

description

These bus buffers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to
provide a TTL interface to a 5-V system environment.

The ’LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the
high-impedance state when the associated output-enable (OE

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V

is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.

CC

However, to ensure the high-impedance state above 1.5 V, OE
the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using I
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.

The SN54LVTH125 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH125 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

) input is high.

should be tied to VCC through a pullup resistor;

and power-up 3-state. The I

off

circuitry

off

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

SN54LVTH125, SN74LVTH125

3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS

SCBS703E – AUGUST 1997 – REVISED APRIL 1999

OE A

FUNCTION TABLE

(each buffer)

INPUTS

L H H
L LL

HXZ

OUTPUT

Y

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, J, and PW packages.

†

1OE

1A

2OE

2A

3OE

3A

4OE

4A

1
2

4
5

10
9

13
12

EN

1

logic diagram (positive logic)

1

1OE

2

1A 1Y

4

2OE

3

3OE

3A 3Y

4OE

10

9

13

3

1Y

6

2Y

8

3Y

11

4Y

8

5

2A 2Y

Pin numbers shown are for the D, DB, J, and PW packages.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6

12

4A 4Y

11

UNIT

SN54LVTH125, SN74LVTH125

3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS

SCBS703E – AUGUST 1997 – REVISED APRIL 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

†

Voltage range applied to any output in the high-impedance

or power-off state, V
Voltage range applied to any output in the high state, V
Current into any output in the low state, I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

: SN54LVTH125 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(see Note 1) –0.5 V to V

O

CC

+ 0.5 V. . . . . . . . . . . . .

SN74LVTH125 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the high state, I

(see Note 2): SN54LVTH125 48 mA. . . . . . . . . . . . . . . . . . . . . . .

O

SN74LVTH125 64 mA. . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Output clamp current, I
Package thermal impedance, θ

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

(see Note 3): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 4)

SN54LVTH125 SN74LVTH125

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V

T

A

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA

Power-up ramp rate 200 200 µs/V

CC

Operating free-air temperature –55 125 –40 85 °C

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54LVTH125, SN74LVTH125

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

3 V

V

V

V

V

V

V

I

A

Data inputs

V

V

V

V

()

V

CC

3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS

SCBS703E – AUGUST 1997 – REVISED APRIL 1999

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LVTH125 SN74LVTH125

MIN TYP†MAX MIN TYP†MAX

V

IK

OH

OL

I

I

off

I

I(hold)

I

OZH

I

OZL

I

OZPU

I

OZPD

I

CC

∆I

CC

C

i

C

o

∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

Control inputs VCC = 3.6 V, VI = VCC or GND ±1 ±1

p

Data inputs

§

VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4

=

CC

= 2.7

CC

= 3

CC

VCC = 0 or 3.6 V, VI = 5.5 V 10 10

= 3.6

CC

VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

= 3

CC

VCC = 3.6 V‡, VI = 0 to 3.6 V ±500
VCC = 3.6 V, VO = 3 V 5 5 µA
VCC = 3.6 V, VO = 0.5 V –5 –5 µA
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,

OE

= don’t care

VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE

= don’t care

=

= 3.6 V,
IO = 0,
VI = VCC or GND

VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND

VI = 3 V or 0 4 4 pF
VO = 3 V or 0 6.5 6.5 pF

IOH = –24 mA 2
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
IOL = 32 mA 0.5 0.5
IOL = 48 mA 0.55
IOL = 64 mA 0.55

VI = V

CC

VI = 0 –5 –5

VI = 0.8 V 75 75
VI = 2 V –75 –75

Outputs high 0.12 0.19 0.12 0.19
Outputs low 4.5 7 4.5 7
Outputs disabled 0.12 0.19 0.12 0.19

1 1

∗

±50

∗

±50

0.3 0.2 mA

±50 µA

±50 µA

µ

µA

mA

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

A

Y

ns

OE

Y

ns

OE

Y

ns

SN54LVTH125, SN74LVTH125

3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS

SCBS703E – AUGUST 1997 – REVISED APRIL 1999

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

SN54LVTH125 SN74LVTH125

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

†

All typical values are at VCC = 3.3 V, TA = 25°C.

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN TYP†MAX MIN MAX

1 4.2 4.7 1 2 3.5 4.5
1 4.1 5.1 1 2.1 3.9 4.9
1 4.9 5.6 1 2 4 5.5

1.1 4.9 5.6 1.1 2.1 4 5.4

1.5 5.3 5.9 1.5 2.3 4.5 5.7

1.3 4.7 4.2 1.3 2.8 4.5 4

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54LVTH125, SN74LVTH125

3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS

SCBS703E – AUGUST 1997 – REVISED APRIL 1999

PARAMETER MEASUREMENT INFORMATION

S1

1.5 V

1.5 V

1.5 V1.5 V

500 Ω

t

w

1.5 V

500 Ω

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

t

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

t

PHL

t

PLH

6 V

Open

GND

2.7 V

0 V

V

OH

V

OL

V

OH

V

OL

2.7 V

0 V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

t

PZL

1.5 V

t

PZH

1.5 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Open

GND

1.5 V

t

6 V

h

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

t

PLZ

t

PHZ

2.7 V

0 V

2.7 V

0 V

2.7 V

0 V

3 V

V

OL

V

OH

≈ 0 V

Figure 1. Load Circuit and Voltage Waveforms

6

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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

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Copyright  1999, Texas Instruments Incorporated