Texas Instruments SN74LVT8980DW, SN74LVT8980DWR Datasheet

SN54LVT8980, SN74LVT8980

EMBEDDED TEST-BUS CONTROLLERS

IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997

D

Members of Texas Instruments (TI) Broad
Family of Testability Products Supporting
IEEE Std 1149.1-1990 (JTAG) Test Access
Port (TAP) and Boundary-Scan Architecture

D

Provide Built-In Access to IEEE Std 1149.1
Scan-Accessible Test/Maintenance
Facilities at Board and System Levels

D

While Powered at 3.3 V, the TAP Interface is
Fully 5-V Tolerant for Mastering Both 5-V
and/or 3.3-V IEEE Std 1149.1 Targets

D

Simple Interface to Low-Cost 3.3-V
Microprocessors/Microcontrollers Via 8-Bit
Asynchronous Read/Write Data Bus

D

Easy Programming Via Scan-Level
Command Set and Smart TAP Control

D

Transparently Generate Protocols to
Support Multidrop TAP Configurations
Using TI’s Addressable Scan Port

D

Flexible TCK Generator Provides
Programmable Division, Gated-TCK, and
Free-Running-TCK Modes

D

Discrete TAP Control Mode Supports
Arbitrary TMS/TDI Sequences for
Non-Compliant Targets

D

Programmable 32-Bit T est Cycle Counter
Allows Virtually Unlimited Scan/Test Length

D

Accommodate Target Retiming (Pipeline)
Delays of Up to 15 TCK Cycles

D

Test Output Enable (TOE) Allows for
External Control of TAP Signals

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)
at TAP Support Backplane Interface and/or
High Fanout

D

Package Options Include Plastic
Small-Outline (DW) Package, Ceramic Chip
Carriers (FK), and Ceramic 300-mil DIPs (JT)

SN54LVT8980...JT PACKAGE

SN74LVT8980. . . DW PACKAGE

STRB

CLKIN

SN54LVT8980. . . FK PACKAGE

D1
D2
D3

NC

GND

D4
D5

NC – No internal connection

(TOP VIEW)

1

R/W

2

D0

3

D1

4

D2

5

D3

6

GND

7

D4

8

D5

9

D6

10

D7

11
12

(TOP VIEW)

D0

R/W

STRB

4 3 2 128

5
6
7
8
9
10
11

12 13 14 15 16 17 18

D7

D6

CLKIN

NC

NC

24
23
22
21
20
19
18
17
16
15
14
13

A0

27 26

TOE

A0
A1
A2
RDY
TDO
V

CC

TCK
TMS
TRST
TDI
RST
TOE

A1

A2

25
24
23
22
21
20
19

TDI

RST

RDY
TDO
V

CC

NC
TCK
TMS
TRST

description

The ’L VT8980 embedded test-bus controllers (eTBC) are members of the TI broad family of testability integrated
circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex
circuit assemblies. Unlike most other devices of this family, the eTBC is not a boundary-scannable device;
rather, its function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command of an
embedded host microprocessor/microcontroller. Thus, the eTBC enables the practical and ef fective use of the
IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and
configuration/maintenance facilities at board and system levels.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1997, Texas Instruments Incorporated

1

SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997

description (continued)

The eTBC masters all T AP signals required to support one 4- or 5-wire IEEE Std 1149.1 serial test bus – test
clock (TCK), test mode select (TMS), test data input (TDI), test data output (TDO), and test reset (TRST). All
such signals can be connected directly to the associated target IEEE Std 1149.1 devices without need for
additional logic or buffering. However , as well as being directly connected, the TMS, TDI, and TDO signals can
be connected to distant target IEEE Std 1149.1 devices via a pipeline, with a retiming delay of up to 15 TCK
cycles; the eTBC automatically handles all associated serial-data justification.

Conceptually, the eTBC operates as a simple 8-bit memory- or I/O- mapped peripheral to a
microprocessor/microcontroller (host). High-level commands and parallel data are passed to/from the eTBC via
its generic host interface, which includes an 8-bit data bus (D7–D0) and a 3-bit address bus (A2–A0). Read/write
select (R/W
of the CLKIN period. An asynchronous ready (RDY) indicator is provided to hold off, or insert wait states into,
a host read/write cycle when the eTBC cannot respond immediately to the requested read/write operation.

High-level commands are issued by the host to cause the eTBC to generate the TMS sequences necessary
to move the test bus from any stable T AP-controller state to any other such stable state, to scan instruction or
data through test registers in target devices, and/or to execute instructions in the Run-Test/Idle TAP state. A
32-bit counter can be programmed to allow a predetermined number of scan or execute cycles.

During scan operations, serial data that appears at the TDI input is transferred into a serial-to-4 × 8-bit-parallel
first-in/first-out (FIFO) read buffer, which can then be read by the host to obtain the return serial-data stream
up to eight bits at a time. Serial data that is to be transmitted from the TDO output is written by the host, up to
eight bits at a time, to a 4 × 8-bit-parallel-to-serial FIFO write buffer.

) and strobe (STRB) signals are implemented so that the critical host-interface timing is independent

In addition to such simple state-movement, scan, and run-test operations, the eTBC supports several additional
commands that provide for input-only scans, output-only scans, recirculate scans (in which TDI is mirrored back
to TDO), and a scan mode that generates the protocols used to support multidrop T AP configurations using TI’s
addressable scan port. Two loopback modes also are supported that allow the microprocessor/microcontroller
host to monitor the TDO or TMS data streams output by the eTBC.

The eTBC’s flexible clocking architecture allows the user to choose between free-running (in which the TCK
always follows CLKIN) and gated modes (in which the TCK output is held static except during state-move,
run-test, or scan cycles) as well as to divide down TCK from CLKIN. A discrete mode is also available in which
the TAP is driven strictly by read/write cycles under full control of the microprocessor/microcontroller host.
These features ensure that virtually any IEEE Std 1 149.1 target device or device chain – even where such may
not fully comply to IEEE Std 1149.1 – can be serviced by the eTBC.

While most operations of the eTBC are synchronous to CLKIN, a test-output enable (TOE
control of the T AP outputs, and a reset (RST) input is provided for hardware reset of the eTBC. The former can
be used to disable the eTBC so that an external controller can master the associated IEEE Std 1 149.1 test bus.

The SN54LVT8980 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVT8980 is characterized for operation from –40°C to 85°C.

) is provided for output

2

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IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

functional block diagram

V

CC

SN54LVT8980, SN74LVT8980

EMBEDDED TEST-BUS CONTROLLERS

SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997

STRB

R/W

A2–A0

D7–D0

14

1

2

22–24

11–8,
6–3

21

RDYRST

V

CC

V

CC

15

TDI

TDI

Buffer

Host

Interface

Command/

Control

TDO

Buffer

TAP-State
Generator

20

17

TDO

TMS

Discrete Control

12

CLKIN

V

CC

13

TOE

Pin numbers shown are for the DW and JT packages.

TCK

Generator

18

16

TCK

TRST

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997

Terminal Functions

TERMINAL

NAME

A2–A0

CLKIN

D7–D0

GND Ground

RDY

RST

R/W

STRB

TCK

TDI

TDO

TMS

TOE

TRST

V

CC

DESCRIPTION

Address inputs. A2–A0 form the 3-bit address bus that interfaces the eTBC to its microprocessor/microcontroller host. These
inputs directly index the eTBC register to be accessed (read from or written to).

Clock input. CLKIN is the system clock input for the eTBC. Most operations of the eTBC are synchronous to CLKIN. Internally,
the CLKIN signal is divided by a programmable divisor to generate TCK.

Data inputs/outputs. D7–D0 form the 8-bit bidirectional data bus that interfaces the eTBC to its
microprocessor/microcontroller host. Data in the eTBC registers is accessed (read or written) using this data bus. D7 is
considered the most-significant bit, while D0 is considered the least-significant bit.

Ready output. RDY is used to indicate to the microprocessor/microcontroller host whether or not the eTBC is ready to service
the access (read or write) operation that is currently being requested. If RDY remains high following the initiation of an access
cycle (STRB
(STRB
may clear the not-ready state, which allows RDY to return high before the end of the access cycle. In any event, the RDY
output returns high upon the termination of any access cycle (STRB

Reset input. RST is used to initiate asynchronous reset of the eTBC. Assertion (low) of RST places the eTBC in a reset state
from which it does not exit until RST
and TRST
connection.

Read/write select. R/W is used by the microprocessor/microcontroller host to instruct the eTBC as to whether it is to perform
read access (R/W
drive low and/or high logic levels onto the host data bus. Otherwise, while R/W
high-impedance state so that the host data bus can drive to the eTBC.

Read/write strobe. STRB is used by the microprocessor/microcontroller host to instruct the eTBC to initiate (STRB negative
edge) or terminate/conclude (STRB
high level if it has no external connection.

Test clock. TCK transmits the TCK signal required by the eTBC’s IEEE Std 1149.1 target(s). All operations of the TAP are
synchronous to TCK. Generally, the TCK signal is generated internally by the eTBC by division of CLKIN by a programmable
divisor. Alternatively, when the eTBC is in its discrete-control mode, a rising edge of TCK is generated on a read to the
discrete-control register, while a falling edge is generated on a write to the discrete-control register.

Test data input. TDI receives the TDI signal output by the eTBC’s IEEE Std 1149.1 target(s). It is the serial input for shifting
test data from the target(s); it is sampled on the rising edge of TCK and is expected to be transferred from the target(s) on
the falling edge of TCK. An internal pullup forces TDI to a high level if it has no external connection.

Test data output. TDO transmits the TDO signal required by the eTBC’s IEEE Std 1149.1 target(s). It is the serial output for
shifting test data to the target(s); it is transferred on the falling edge of TCK and is sampled in the target on the rising edge
of TCK.

T est mode select. TMS transmits the TMS signal required by the eTBC’s IEEE Std 1 149.1 target(s). It is the one control signal
that directs the next TAP-controller state of the target(s). It is transferred from the eTBC on the falling edge of TCK and is
sampled in the target(s) on the rising edge of TCK.

T est-output enable. TOE is the active-low output enable for the eTBC TAP outputs (TCK, TDO, TMS, TRST). When TOE is
inactive (high) the TAP outputs are disabled to a high-impedance state. Otherwise, when TOE
are enabled to drive low and/or high logic levels according to other eTBC functions. An internal pullup forces TOE
level if it has no external connection.

Test reset. TRST transmits the TRST signal that may be required by some of the eTBC’s IEEE Std 1149.1 target(s). A low
signal at TRST
generated only when the microprocessor/microcontroller host writes an appropriate value into the eTBC command register
or, while the eTBC is in discrete-control mode, into the discrete-control register.

Supply voltage

negative edge) then the eTBC is ready. Otherwise, if RDY goes low following the initiation of an access cycle

negative edge) then the eTBC is not ready. In cases where the eTBC is not ready , subsequent processing in the eTBC

positive edge).

is released (high). While RST is low, the eTBC ignores host writes, the RDY, TDO, TMS,

outputs are high, while TCK outputs CLKIN/16. An internal pullup forces RST to a high level if it has no external

high) or write access (R/W low). While R/W is high and STRB is low, the D7-D0 outputs are enabled to

is low, the D7–D0 outputs are disabled to a

positive edge) an access (read or write) operation. An internal pullup forces STRB to a

is active (low), the TAP outputs

to a high

is intended to initiate asynchronous test reset of the connected target(s). Such a low signal at TRST is

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVT8980, SN74LVT8980

EMBEDDED TEST-BUS CONTROLLERS

IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997

application information

In application, the eTBC is used to master a single IEEE Std 1149.1 TAP under the control of a
microprocessor/microcontroller host. A typical implementation is shown in Figure 1.

TCK
TMS
TDO
TDI
TRST

IEEE
Std 1149.1­Compliant

Device Chain

(Target)

Microprocessor/

Microcontroller

(Host)

STRB

RDY

A (2–0)

D (7–0)

RST

R/W

’LVT8980

Embedded

Test
Bus

Controller

CLKIN TOE

CS

OSC

Program/Vector

Memory

(ROM/RAM)

(If/As Required)

GND

Figure 1. eTBC Application

All signals required to master IEEE Std 1149.1-compliant devices – TCK, TMS, TDO, TDI – are
sourced/received by the eTBC. The eTBC can also source the optional TRST signal. Additionally, the eTBC
implements high-drive output buffers, allowing it to interface directly to on- or off-board targets without need for
buffering or other additional logic.

The eTBC’s generic host interface allows it to act as a simple 8-bit memory- or I/O-mapped peripheral. As shown
in Figure 1, for many choices of host microprocessor/microcontroller, this interface can be accomplished without
additional logic. While the eTBC requires a clock input (CLKIN), in many cases it can be driven from the same
source that provides a clock signal to the host.

Thus, in combination with the host microprocessor/microcontroller, the eTBC can be used to implement a
two-chip embedded test-control function supporting board- and system-level built-in test based on structured
IEEE Std 1149.1 test access. In some cases, for additional program and/or test vector storage, an external
ROM/RAM may be required.

By use of the eTBC in such an embedded test control function, the host microprocessor/microcontroller is freed
from the burden of generating the T AP-state sequences, serializing the outgoing bit stream, and deserializing
the incoming bit stream. All such tasks are implemented in the eTBC, allowing the host to operate at full 8-bit
parallel efficiency, host software to operate at the level of discrete scan operations versus the level of TAP
manipulation, and test throughput to be maximized. The eTBC’s full suite of data-scan and instruction-scan
commands ensure that the host software operates efficiently.

Host efficiency and flexibility is also maximized through the eTBC’s fully visible status and implementation of
the ready output (RDY). RDY goes inactive during a read or write access if the host-requested access cannot
be performed immediately . Thus, it can be used to insert hold or wait states back to the host. When the condition
blocking the access clears, the requested access completes. Additionally, all conditions that can cause such
a blocking condition are continuously updated in the eTBC status and command registers. Thus, the host
software can poll the eTBC status rather than implement RDY in hardware.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997

application information (continued)

The eTBC also provides several capabilities that support special target application requirements. The eTBC’s
test-output enable allows its master function to be disabled so that another device (an external tester, for
example) can control the target TAP. Where required, due to target non-compliance or sensitivity to state
sequencing, discrete-control mode provides the host software with arbitrary control of TMS and TDO
sequences. Also, where targets may be sensitive to leaving Shift-DR state during scan operation, gated-TCK
mode allows the TCK output to be stopped, rather than cycling the target T AP state to Pause-DR state, when
service to TDI buffer or TDO buffer is required.

Where target devices are extremely distant (due to cabling, etc.), pipelining may be implemented at intervals
along the incoming or outgoing paths to retime (deskew) the TDI, TDO, and TMS signals. An example is shown
in Figure 2. In such applications, the eTBC can automatically adjust the incoming test-data bit stream to account
for cycle delays introduced by the pipeline.

’LVT8980

eTBC

TCK

TMS
TDO

TDI

C1

1D
1D

1D

Distant

IEEE

Std

1149.1-

Compliant

Device

Chain

Figure 2. Retimed Interface to Target

Also, in gated-TCK mode, special scan commands provide transparent support for addressable shadow
protocols. Thus, in conjunction with its high-drive outputs, the eTBC can fully support multidrop backplane T AP
configurations implemented with TI’s addressable scan ports (ASP). Figure 3 shows a multidrop TAP
configuration in a passive-backplane application implemented with a centralized (one eTBC per chassis/rack)
test-control architecture, while Figure 4 shows a passive-backplane application implemented with a distributed
(eTBC per module) test-control architecture. Figure 5 shows a multidrop TAP configuration in an
active-backplane (motherboard) application.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVT8980, SN74LVT8980

EMBEDDED TEST-BUS CONTROLLERS

IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997

Plug-In Module

IEEE Std 1149.1-Compliant

Device Chain

STCK

STDI

ASP

(Host)

PTCK

Microcontroller

Microprocessor/

’LVT8980

etBC

PTDO

TDI
TCK

TMS
TDO
TRST

STDO

STMS

PTDI

PTMS

STRST

PTRST

Plug-In Module

IEEE Std 1149.1-Compliant

Device Chain

STDO

STMS

STCK

STDI

ASP

PTDI

PTCK

PTMS

PTDO

STRST

PTRST

Plug-In Module

IEEE Std 1149.1-Compliant

Device Chain

STDO

STMS

STCK

STDI

ASP

PTDI

PTCK

PTMS

PTDO

STRST

PTRST

To
Other
Modules

Passive Backplane

Figure 3. Passive-Backplane Application With Centralized (eTBC Per Chassis) Test-Control Architecture

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997

Plug-In Module

IEEE Std 1149.1-Compliant

Device Chain

STCK

STDI

ASP

(Host)

PTCK

Microcontroller

Microprocessor/

’LVT8980

etBC

PTDO

TDI
TCK

TMS
TDO
TRST

STDO

STMS

PTDI

PTMS

STRST

PTRST

Plug-In Module

IEEE Std 1149.1-Compliant

Device Chain

STCK

STDI

ASP

(Host)

PTCK

Microcontroller

Microprocessor/

’LVT8980

etBC

PTDO

TDI
TCK

TMS
TDO
TRST

STDO

STMS

PTDI

PTMS

STRST

PTRST

Plug-In Module

IEEE Std 1149.1-Compliant

Device Chain

STCK

STDI

ASP

(Host)

PTCK

Microcontroller

Microprocessor/

’LVT8980

etBC

PTDO

TDI
TCK

TMS
TDO
TRST

STDO

STMS

PTDI

PTMS

STRST

PTRST

To

Other

Modules

Passive Backplane

To
Other
Modules

Figure 4. Passive-Backplane Application With Distributed Test-Control (eTBC Per Card) Architecture

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVT8980, SN74LVT8980

EMBEDDED TEST-BUS CONTROLLERS

IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997

’LVT8980

(Host)

Microcontroller

Microprocessor/

etBC

TDI
TCK

TMS
TDO
TRST

Plug-In Module

IEEE

Std

1149.1-Compliant
Device Chain

STRST

STDO

STMS

STCK

STDI

ASP

PTDI

PTCK

PTMS

PTDO

Active Backplane (Motherboard)

PTRST

Plug-In Module

IEEE

Std

1149.1-Compliant
Device Chain

STRST

STDO

STMS

STCK

STDI

ASP

PTDI

PTCK

PTMS

PTDO

PTRST

Plug-In Module

IEEE

Std

1149.1-Compliant
Device Chain

STRST

STDO

STMS

STCK

STDI

ASP

PTDI

PTCK

PTMS

PTDO

PTRST

To
Other
Modules

Figure 5. Active-Backplane (Motherboard) Application

architecture

Conceptually, the eTBC can be viewed as an IEEE Std 1149.1 coprocessor/accelerator that operates in
conjunction with (and under the control of) a host microprocessor/microcontroller. The eTBC implements this
function using an 8-bit generic host interface and a scan-test-based command/control architecture. As shown
in the functional block diagram, beyond these fundamental elements and another central block supporting
discrete-control mode, the eTBC functions are accomplished in four additional blocks – one for each of the
required TAP signals – a TCK generator, a TAP-state (TMS) generator, a TDO buffer, and a TDI buffer.

host interface

The eTBC host interface is implemented generically on an 8-bit read/write data bus (D7–D0). Three address
pins (A2–A0) directly index the eTBC’s eight read/write registers: configurationA, configurationB, status,
command, TDO buffer , TDI buffer, counter, and discrete control. The register address map is given in Table 1.

host access timing

Host access timing is asynchronous to the clock input (CLKIN) and is fully controlled by the read/write strobe
(STRB). The read/write select (R/W) serves to control the direction of data flow on the bidirectional data bus.
Figure 6 shows the read access timing while Figure 7 shows the write access timing. As shown, for either read
or write access, R/W

For read access (R/W high) the eTBC data bus outputs are made active, on the falling edge of STRB, to drive
the data contained in the selected eTBC register. Otherwise, when STRB is high, the eTBC data outputs are
at high impedance. Therefore, in many applications, the R/W signal can be shared in common with other host
peripherals (ROM or RAM, for example) while the STRB signal is generated separately (by discrete chip-select
signals available from the host or a decode logic) for each required peripheral.

and address signals should be held while STRB is low.

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9

SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997

host access timing (continued)

For write access (R/W low), the eTBC data outputs remain at high impedance independent of STRB. The
address of the register to be written is latched from the address pins on the falling edge of STRB, while the data
to be written is latched from the data bus on the rising edge of STRB.

STRB

t

h

R/W

t

su

A

D

RDY

STRB

R/W

t

PZH

t

su

Valid

or t

PZL

t

PHL

t

PHZ

or t

PLZ

t

h

t

PLH

Figure 6. Read Access Timing

t

t

su

h

10

RDY

t

su

A

D

t

PHL

Valid

t

su

Valid

t

h

t

h

t

PLH

Figure 7. Write Access Timing

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVT8980, SN74LVT8980

EMBEDDED TEST-BUS CONTROLLERS

IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997

ready output

The ready output (RDY) from the host interface can be used, where the selected microprocessor/microcontroller
supports it, to insert wait or hold states back to the host. If a host-requested access cannot be performed
immediately , RDY goes inactive (low) during that given access. When the condition blocking the access clears,
RDY goes active (high) and the eTBC grants the requested access. Alternatively, where such
hardware-generated hold or wait states are not supported in the selected microprocessor/microcontroller host,
the eTBC status and/or command registers can be polled to determine its readiness to grant a given read or
write access.

Conditions that cause a host access to be blocked (and RDY to become inactive) are limited to the following:

D

While the TDI buffer is empty, as indicated in status register (bit 7, TDIS), a requested read to TDI-buffer
register generates RDY inactive; this condition clears, RDY goes active, and the requested access
completes, when the TDI buffer is no longer empty.

D

While the TDO buffer is full or is being reset upon initiation of a scan command, as indicated in status register
(bit 6, TDOS), a requested write to TDO-buffer register generates RDY inactive; this condition clears, RDY
goes active, and the requested access completes, when the TDO buffer is no longer full or the TDO-buffer
reset completes, as applicable.

D

While a command is in progress, as indicated by a non-zero value in the opcode field (bits 3–0, OPCOD)
of the command register, a requested write to command, configurationA, configurationB, or counter
registers generates RDY inactive. This condition clears, RDY goes active, and the requested access is
complete, when the previously specified command finishes. The sole exception is the writing of a logic 1
into the software reset (bit 7, SWRST) bit of the command register, which is never blocked.

D

While a full-duplex scan command is in progress, and the number of retiming-delay bits is other than zero,
the number of writes to TDO-buffer register may not exceed, by more than 5, the number of reads to
TDI-buffer register . A write to TDO-buffer register that does exceed this limit is blocked, and generates RDY
inactive, indefinitely; the TDI-buffer register must be read before another write to TDO-buffer register.

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