Texas Instruments SN74LVT573PWR, SN74LVT573DBLE, SN74LVT573DBR, SN74LVT573DW, SN74LVT573DWR Datasheet
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SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MA Y 1992 – REVISED JULY 1995
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static Power
Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical V
< 0.8 V at V
D
ESD Protection Exceeds 2000 V Per
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
D
Support Live Insertion
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Packages, and Ceramic
(J) DIPs
description
SN54LVT573...J OR W PACKAGE
SN74LVT573. . . DB, DW, OR PW PACKAGE
SN54LVT573. . . FK PACKAGE
3D
4D
5D
6D
7D
(TOP VIEW)
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
(TOP VIEW)
2D1DOE
3 2 1 20 19
4
5
6
7
8
910111213
8D
1
2
3
4
5
6
7
8
9
10
GND
LE
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
V
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
1Q
18
17
16
15
14
7Q
CC
2Q
3Q
4Q
5Q
6Q
These octal latches are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to
provide a TTL interface to a 5-V system environment.
The eight latches of the ’L VT573 are transparent D-type latches. While the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up
at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components. OE does not affect the internal operations of the latches.
Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74L VT573 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54L VT573 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LVT573 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1995, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MA Y 1992 – REVISED JULY 1995
FUNCTION TABLE
(each latch)
INPUTS
OE LE D
L H H H
L HL L
L LX Q
H X X Z
OUTPUT
Q
0
logic symbol
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
†
1
11
2
3
4
5
6
7
8
9
EN
C1
1D
19
18
17
16
15
14
13
12
logic diagram (positive logic)
1
OE
11
LE
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2
To Seven Other Channels
C1
1D
19
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Voltage range applied to any output in the high state or power-off state, V
Current into any output in the low state, IO: SN54LVT573 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
Input clamp current, I
Output clamp current, I
Maximum power dissipation at TA = 55°C (in still air) (see Note 3):DB package 0.6 W. . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Data Book
, literature number SCBD002B.
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 1) –0.5 V to 7 V. . . .
O
SN74LVT573 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): SN54LVT573 48 mA. . . . . . . . . . . . . . . . . . . . . . . . .
O
SN74LVT573 64 mA. . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
DW package 1.6 W. . . . . . . . . . . . . . . . . . .
PW package 0.7 W. . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS T echnology
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MA Y 1992 – REVISED JULY 1995
recommended operating conditions (see Note 4)
SN54LVT573 SN74LVT573
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T
A
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 °C
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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