Texas Instruments SN74LVT245BDBLE, SN74LVT245BDBR, SN74LVT245BDW, SN74LVT245BDWR, SN74LVT245BPWLE Datasheet

SN54LVT245B, SN74LVT245B

3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCES004D – JANUARY 1995 – REVISED APRIL 2000

D

State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation

D

Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V

D

Support Unregulated Battery Operation
Down to 2.7 V

D

Typical V

(Output Ground Bounce)

OLP

<0.8 V at VCC = 3.3 V, TA = 25°C

D

I

and Power-Up 3-State Support Hot

off

Insertion

D

Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II

D

ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Packages, and Ceramic
(J) DIPs

CC

SN54LVT245B...J OR W PACKAGE

SN74LVT245B. .. DB, DW, OR PW PACKAGE

)

SN54LVT245B. . . FK PACKAGE

A3
A4
A5
A6
A7

(TOP VIEW)

1

DIR

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

GND

10

(TOP VIEW)

A2A1DIR

3212019

4
5
6
7
8

910111213

20
19
18
17
16
15
14
13
12

V

CC

OE
B1
B2
B3
B4
B5
B6
B7

11

B8

CC

OE

V

B1

18

B2

17
16

B3

15

B4

14

B5

description

These octal bus transceivers are designed
specifically for low-voltage (3.3-V) V

CC

A8

operation,

GND

B8

B7

B6

but with the capability to provide a TTL interface
to a 5-V system environment.

These devices are designed for asynchronous communication between data buses. They transmit data from
the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the devices so the buses are effectively isolated.

When VCC is between 0 and 1.5 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using I

and power-up 3-state. The I

off

disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.

The SN54LVT245B is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVT245B is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

circuitry

off

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

1

SN54LVT245B, SN74LVT245B

OPERATION

3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCES004D – JANUARY 1995 – REVISED APRIL 2000

INPUTS

OE DIR

L L B data to A bus
L H A data to B bus

H X Isolation

FUNCTION TABLE

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

OE

DIR

A1

A2
A3
A4
A5
A6
A7
A8

19
1

2

3
4
5
6
7
8
9

G3
3EN1[BA]

3EN2[AB]

1

2

logic diagram (positive logic)

1

DIR

18

17
16
15
14
13
12
11

B1

B2
B3
B4
B5
B6
B7
B8

A1

19

OE

2

18

B1

To Seven Other Channels

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

SN54LVT245B, SN74LVT245B

3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCES004D – JANUARY 1995 – REVISED APRIL 2000

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high-impedance

or power-off state, V

Voltage range applied to any output in the high state, V

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(see Note 1) –0.5 V to V

O

CC

+ 0.5 V. . . . . . . . . . . . .

Current into any output in the low state, IO: SN54LVT245B 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74LVT245B 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the high state, I

(see Note 2): SN54LVT245B 48 mA. . . . . . . . . . . . . . . . . . . . . . . .

O

SN74LVT245B 64 mA. . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Output clamp current, I
Package thermal impedance, θ

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

(see Note 3): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 4)

SN54LVT245B SN74LVT245B

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V

T

A

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA

Power-up ramp rate 200 200 µs/V

CC

Operating free-air temperature –55 125 –40 85 °C

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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