Texas Instruments SN74LVT16952DGGR, SN74LVT16952DL, SN74LVT16952DLR Datasheet
SN54LVT16952, SN74LVT16952
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS151D – MAY 1992 – REVISED AUGUST 1996
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
D
Members of the Texas Instruments
Widebus
D
Support Mixed-Mode Signal Operation (5-V
Family
Input and Output Voltages With 3.3-V VCC)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model
(C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
D
Support Live Insertion
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes
PCB Layout
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
SN54LVT16952. . . WD PACKAGE
SN74LVT16952. . . DGG OR DL PACKAGE
1OEAB
1CLKAB
1CLKENAB
2CLKENAB
2CLKAB
2OEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1CLKBA
1CLKENBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CLKENBA
2CLKBA
2OEBA
The ’L VT16952 are 16-bit registered transceivers designed for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the A or B bus is stored in the registers on the low-to-high
transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB
or CLKENBA) input
is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74L VT16952 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages,
which provide twice the I/O pin count and functionality of standard small-outline packages in the same
printed-circuit-board area.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
SN54LVT16952, SN74LVT16952
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS151D – MAY 1992 – REVISED AUGUST 1996
description (continued)
The SN54L VT16952 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVT16952 is characterized for operation from –40°C to 85°C.
logic symbol
†
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
56
54
55
1
3
2
29
31
30
28
26
27
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
EN3
G1
EN4
G2
2C6
EN9
G7
EN10
G8
3
6D
9
12D
5D
4
11D
10
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1OEBA
1CLKENBA
1CLKBA 1C5
1OEAB
1CLKENAB
1CLKAB
2OEBA
2CLKENBA
2CLKBA 7C11
2OEAB
2CLKENAB
2CLKAB 8C12
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT16952, SN74LVT16952
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS151D – MAY 1992 – REVISED AUGUST 1996
logic diagram (positive logic)
1A1
3
2
56
One of Eight
Channels
5
1CLKENAB 1CLKENBA
1CLKAB
1OEBA
C1
CE
1D
†
OUTPUT
A
B
0
0
FUNCTION TABLE
INPUTS
CLKENAB
H X L X B
X LLXB
L ↑ LL L
L ↑ LH H
X X H X Z
†
A-to-B data flow is shown; B-to-A data flow is similar
but uses CLKENBA
‡
Level of B before the indicated steady-state input
conditions were established
CLKAB
OEAB
, CLKBA, and OEBA.
‡
‡
54
55
1CLKBA
1
1OEAB
52
1B1
C1
CE
1D
To Seven Other Channels
2A1
26
27
29
One of Eight
15
Channels
C1
CE
1D
C1
CE
1D
To Seven Other Channels
2CLKENAB
2CLKAB 2CLKBA
2OEBA
31
2CLKENBA
30
28
2OEAB
42
2B1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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