Texas Instruments SN74LVT16646DGGR, SN74LVT16646DL, SN74LVT16646DLR Datasheet
SN54LVT16646, SN74LVT16646
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS149C – JULY 1994 – REVISED JULY 1995
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
D
Members of the Texas Instruments
Widebus
D
Support Mixed-Mode Signal Operation (5-V
Family
Input and Output Voltages With 3.3-V VCC)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
D
Support Live Insertion
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes
PCB Layout
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
SN54LVT16646. . . WD PACKAGE
SN74LVT16646. . . DGG OR DL PACKAGE
1CLKAB
2CLKAB
1DIR
1SAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2SAB
2DIR
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OE
1CLKBA
1SBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2SBA
2CLKBA
2OE
The ’LVT16646 are 16-bit bus transceivers designed for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked
into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the ′LVT16646.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition
between stored and real-time data. The direction control (DIR) determines which bus receives data when OE
is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the
other register.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
SN54LVT16646, SN74LVT16646
OPERATION OR FUNCTION
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS149C – JULY 1994 – REVISED JULY 1995
description (continued)
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74L VT16646 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages,
which provide twice the I/O pin count and functionality of standard small-outline packages in the same
printed-circuit-board area.
The SN54L VT16646 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVT16646 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE DIR CLKAB CLKBA SAB SBA A1 THRU A8 B1 THRU B8
X X ↑ X X X Input Unspecified
X XX ↑ X X Unspecified
H X ↑ ↑ X X Input Input Store A and B data
H X H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus
†
The data output functions may be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled; i.e., data at
the bus pins will be stored on every low-to-high transition of the clock inputs.
DATA I/Os
†
†
Input Store B, A unspecified
Store A, B unspecified
†
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT16646, SN74LVT16646
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS149C – JULY 1994 – REVISED JULY 1995
BUS A
DIRLCLKABXCLKBAXSABXSBA
OE
L
REAL-TIME TRANSFER
BUS B TO BUS A
BUS B
L
OE
L
BUS A
DIRHCLKABXCLKBAXSABLSBA
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
X
BUS A
DIRXCLKAB CLKBAXSABXSBA
X
X
H
X
X
↑
XX
STORAGE FROM
A, B, OR A AND B
↑
↑↑
BUS B
OEOE
X
X
X
X
BUS A
DIRLCLKABXCLKBA
L
L H H or L X H X
TRANSFER STORED DA TA
Figure 1. Bus-Management Functions
H or L
TO A AND/OR B
BUS B
SABXSBA
H
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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