SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MA Y 1992 – REVISED JULY 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
D
Members of the Texas Instruments
Widebus
Family
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
T ypical V
OLP
(Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
D
Support Live Insertion
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes
PCB Layout
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’L VT16543 are 16-bit registered transceivers designed for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or
OEBA
) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB
) input must be low in order to enter data from A or to output data from B. If CEAB
is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts
the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect
the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA,
LEBA, and OEBA inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Copyright 1995, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Widebus is a trademark of Texas Instruments Incorporated.
SN54LVT16543. . . WD PACKAGE
SN74LVT16543. . . DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEAB
1LEAB
1CEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2CEAB
2LEAB
2OEAB
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MA Y 1992 – REVISED JULY 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74L VT16543 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages,
which provide twice the I/O pin count and functionality of standard small-outline packages in the same
printed-circuit-board area.
The SN54L VT16543 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVT16543 is characterized for operation from –40°C to 85°C.
logic symbol
†
1A2
6
1A3
8
1A4
9
1A5
10
1A6
12
1A7
13
1A8
14
2A2
16
2A3
17
2A4
19
2A5
20
2A6
21
2A7
23
2A8
24
15
2A1
8C12
27
5
1A1
6D
1B6
45
1B7
44
1B8
43
1B2
51
1B3
49
1B4
48
1B5
47
1B1
52
5D
3
4
G8
26
8EN10
28
7C11
30
G7
31
7EN9
29
2C6
2
G2
3
2EN4
1
1C5
55
G1
54
1EN3
56
12D
2B6
36
2B7
34
2B8
33
2B2
41
2B3
40
2B4
38
2B5
37
2B1
42
11D
9
10
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MA Y 1992 – REVISED JULY 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1
1B1
C1
1D
C1
1D
56
54
55
1
3
2
5
52
To Seven Other Channels
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A1
2B1
C1
1D
C1
1D
29
31
30
28
26
27
15
42
To Seven Other Channels
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MA Y 1992 – REVISED JULY 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
†
(each 8-bit section)
INPUTS
OUTPUT
CEAB LEAB OEAB A
B
H X X X Z
X XHX Z
L HLXB
0
‡
L LLL L
L L L H H
†
A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA
, LEBA, and OEBA.
‡
Output level before the indicated steady-state input
conditions were established
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
§
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state, V
O
(see Note 1) –0.5 V to 7 V. . . .
Current into any output in the low state, I
O
: SN54LVT16543 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVT16543 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
O
(see Note 2): SN54LVT16543 48 mA. . . . . . . . . . . . . . . . . . . . . . .
SN74LVT16543 64 mA. . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 3):DGG package 1 W. . . . . . . . . . . . . . . . . . .
DL package 1.4 W. . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
§
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS T echnology
Data Book
, literature number SCBD002B.
recommended operating conditions (see Note 4)
SN54LVT16543 SN74LVT16543
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 2.7 3.6 2.7 3.6 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 5.5 5.5 V
I
OH
High-level output current –24 –32 mA
I
OL
Low-level output current 48 64 mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MA Y 1992 – REVISED JULY 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVT16543 SN74LVT16543
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = MIN to MAX‡, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = – 8 mA 2.4 2.4
V
OH
IOH = – 24 mA 2
V
V
CC
=
3 V
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
V
CC
= 2.7
V
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
V
OL
IOL = 32 mA 0.5 0.5
V
V
CC
= 3
V
IOL = 48 mA 0.55
IOL = 64 mA 0.55
VCC = 3.6 V, VI = VCC or GND
p
±1 ±1
VCC = 0 or MAX‡, VI = 5.5 V
Control inputs
10 10
I
I
VI = 5.5 V
20 20
µA
VCC = 3.6 V
VI = V
CC
A or B ports
§
5 5
VI = 0 –10 –10
I
off
VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
VI = 0.8 V
p
75 75
I
I(hold)
V
CC
= 3
V
VI = 2 V
A or B ports
–75 –75
µ
A
I
OZH
VCC = 3.6 V, VO = 3 V 1 1 µA
I
OZL
VCC = 3.6 V, VO = 0.5 V –1 –1 µA
Outputs high 0.12 0.12
I
CC
VCC = 3.6 V, IO = 0,
Outputs low 5 5
mA
V
I
=
V
CC
or
GND
Outputs disabled 0.12 0.12
∆I
CC
¶
VCC = 3 V to 3.6 V , One input at VCC – 0.6 V,
Other inputs at VCC or GND
0.2 0.2 mA
C
i
VI = 3 V or 0 4 4 pF
C
io
VO = 3 V or 0 13 13 pF
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§
Unused pins at VCC or GND
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MA Y 1992 – REVISED JULY 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVT16543 SN74LVT16543
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
t
w
Pulse duration, LEAB or LEBA low 3.3 3.3 3.3 3.3 ns
A or B before LEAB↑ or
Data high 0.8 0.5 0.8 0.5
LEBA↑
Data low 1.5 1.9 1.5 1.9
ns
t
su
Set
up time
A or B before CEAB
↑
or
Data high 0.7 0.4 0.7 0.4
CEBA↑
Data low 1.6 1.9 1.6 1.9
ns
A or B after LEAB↑ or
Data high 0.8 0 0.8 0
LEBA↑
Data low 1.2 1.3 1.2 1.3
ns
t
h
Hold time
A or B after CEAB↑ or
Data high 0.8 0 0.8 0
CEBA↑
Data low 1.3 1.4 1.3 1.4
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVT16543 SN74LVT16543
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
t
PLH
1.4 5 5.8 1.4 2.7 4.6 5.5
t
PHL
A or B
B or A
1.3 4.7 5.9 1.3 2.9 4.6 5.8
ns
t
PLH
1.3 6.8 8.5 1.7 3.7 6.3 8.1
t
PHL
LE
A or B
1.5 6.5 8.3 1.9 3.7 6 7.8
ns
t
PZH
1.4 6 7.7 1.5 3.3 5.8 7.6
t
PZL
OE
A or B
1.6 6.3 8.4 1.6 3.3 6.2 8.2
ns
t
PHZ
2 6.7 7.3 2 4.1 6.5 7.1
t
PLZ
OE
A or B
2.7 6 6.2 2.7 3.9 5.8 5.9
ns
t
PZH
1.4 6.2 7.7 1.5 3.3 6 7.6
t
PZL
CE
A or B
1.6 6.6 8.5 1.7 3.3 6.4 8.3
ns
t
PHZ
2 6.6 7.2 2 4.1 6.4 7.1
t
PLZ
CE
A or B
2.6 5.6 5.9 2.6 4 5.4 5.6
ns
†
All typical values are at VCC = 3.3 V, TA = 25°C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MA Y 1992 – REVISED JULY 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR OUTPUTS
S1
6 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input
1.5 V
2.7 V
0 V
1.5 V 1.5 V
2.7 V
0 V
2.7 V
0 V
1.5 V 1.5 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
1.5 V 1.5 V
2.7 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V
1.5 V
3 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
[
0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...