Datasheet SN74LVT16501DGGR, SN74LVT16501DL, SN74LVT16501DLR, SNJ54LVT16501WD Datasheet (Texas Instruments)

SN54LVT16501, SN74LVT16501

3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS147G – MAY 1992 – REVISED NOVEMBER 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation

D

Members of the Texas Instruments

Widebus

 Family

D

Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)

D

Support Unregulated Battery Operation
Down to 2.7 V

D

UBT

 (Universal Bus Transceiver)

Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode

D

T ypical V

OLP

(Output Ground Bounce)

< 0.8 V at VCC = 3.3 V, TA = 25°C

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model
(C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Support Live Insertion

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes
PCB Layout

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

description

The ’L VT16501 are 18-bit universal bus transceivers designed for low-voltage (3.3-V) VCC operation, but with
the capability to provide a TTL interface to a 5-V system environment.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high,
the outputs are active. When OEAB is low, the outputs are in the high-impedance state.

Copyright  1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and UBT are trademarks of Texas Instruments Incorporated.

SN54LVT16501.. . WD PACKAGE

SN74LVT16501.. . DGG OR DL PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

OEAB

LEAB

A1

GND

A2
A3

V

CC

A4
A5
A6

GND

A7
A8

A9
A10
A11
A12

GND

A13
A14
A15

V

CC

A16
A17

GND

A18

OEBA

LEBA

GND
CLKAB
B1
GND
B2
B3
V

CC

B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V

CC

B16
B17
GND
B18
CLKBA
GND

SN54LVT16501, SN74LVT16501

3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS147G – MAY 1992 – REVISED NOVEMBER 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver. OE
should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the
current-sourcing capability of the driver.

The SN74L VT16501 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages,
which provide twice the input/output (I/O) pin count and functionality of standard small-outline packages in the
same printed circuit board area.

The SN54L VT16501 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVT16501 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

†

INPUTS

OUTPUT

OEAB LEAB CLKAB A

B

L X X X Z
H HXLL
H HXHH
H L ↑ LL
H L ↑ HH
H LHXB

0

‡

H L L X B

0

§

†

A-to-B data flow is shown; B-to-A flow is similar but
uses OEBA

, LEBA, and CLKBA.

‡

Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was high before LEAB went low

§

Output level before the indicated steady-state input
conditions were established

SN54LVT16501, SN74LVT16501

3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS147G – MAY 1992 – REVISED NOVEMBER 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

A2

5

EN1

1

OEAB

2C3

3D

3

A1 B1

54

A14

20

A15

21

A16

23

A17

24

A8

13

A9

14

A10

15

A11

16

A12

17

A3

6

A4

8

A5

9

A6

10

A7

12

B13

38

B14

37

B15

36

B16

34

B17

33

B18

31

6D

4

A18

26

B8

44

B9

43

B10

42

B11

41

B12

40

B3

51

B4

49

B5

48

B6

47

B7

45

B2

52

C6

28

LEBA

G5

30

CLKBA

EN4

27

C3

2

LEAB

G2

55

CLKAB

5C6

OEBA

11

1

A13

19

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

SN54LVT16501, SN74LVT16501

3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS147G – MAY 1992 – REVISED NOVEMBER 1996

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1D
C1

CLK

1D
C1

CLK

B1

OEAB

CLKAB

LEAB

LEBA

CLKBA

OEBA

A1

1

55

2

28

30

27

3

54

To 17 Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state or power-off state, V

O

(see Note 1) –0.5 V to 7 V. . . .

Current into any output in the low state, IO: SN54LVT16501 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74LVT16501 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the high state, I

O

(see Note 2): SN54LVT16501 48 mA. . . . . . . . . . . . . . . . . . . . . . .

SN74LVT16501 64 mA. . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(V

O

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum power dissipation at TA = 55°C (in still air) (see Note 3):DGG package 1 W. . . . . . . . . . . . . . . . . . .

DL package 1.4 W. . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the

Package Thermal Considerations

application note in the

ABT Advanced BiCMOS T echnology Data

Book

.

SN54LVT16501, SN74LVT16501

3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS147G – MAY 1992 – REVISED NOVEMBER 1996

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 4)

SN54LVT16501 SN74LVT16501

MIN MAX MIN MAX

UNIT

V

CC

Supply voltage 2.7 3.6 2.7 3.6 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.8 0.8 V

V

I

Input voltage 5.5 5.5 V

I

OH

High-level output current –24 –32 mA

I

OL

Low-level output current 48 64 mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 4: Unused control inputs must be held high or low to prevent them from floating.

SN54LVT16501, SN74LVT16501

3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS147G – MAY 1992 – REVISED NOVEMBER 1996

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LVT16501 SN74LVT16501

PARAMETER

TEST CONDITIONS

MIN TYP†MAX MIN TYP†MAX

UNIT

V

IK

VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4

V

OH

IOH = –24 mA 2

V

V

CC

=

3 V

IOH = –32 mA 2
IOL = 100 µA 0.2 0.2

V

CC

= 2.7

V

IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4

V

OL

IOL = 32 mA 0.5 0.5

V

V

CC

= 3

V

IOL = 48 mA 0.55
IOL = 64 mA 0.55

p

VCC = 3.6 V, VI = VCC or GND ±1 ±1

Control pins

VCC = 0 or 3.6 V, VI = 5.5 V 10 10

I

I

VI = 5.5 V 120 20

µA

A or B ports‡VCC = 3.6 V

VI = V

CC

1 1

VI = 0 –5 –5

I

off

VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

p

VI = 0.8 V 75 75

I

I(hold)

A or B ports

V

CC

= 3

V

VI = 2 V –75 –75

µ

A

I

OZH

VCC = 3.6 V, VO = 3 V 1 µA

I

OZL

VCC = 3.6 V, VO = 0.5 V –1 µA

Outputs high 0.12 0.12

I

CC

VCC = 3.6 V, IO = 0,

Outputs low 5 5

mA

V

I

=

V

CC

or

GND

Outputs disabled 0.12 0.12

∆I

CC

§

VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND

0.2 0.2 mA

C

i

VI = 3 V or 0 3.5 3.5 pF

C

io

VO = 3 V or 0 12 12 pF

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

Unused pins at VCC or GND

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

SN54LVT16501, SN74LVT16501

3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS147G – MAY 1992 – REVISED NOVEMBER 1996

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)

SN54LVT16501 SN74LVT16501

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN MAX MIN MAX MIN MAX MIN MAX

f

clock

Clock frequency 0 150 0 125 0 150 0 125 MHz

LE high 3.3 3.3 3.3 3.3

twPulse duration

CLK high or low 3.3 3.3 3.3 3.3

ns

A before CLKAB↑ 1.6 2.1 1.6 2.1
B before CLKBA↑ 1.6 2.1 1.6 2.1

tsuSet

up time

A or B before LE↓, CLK high

3.1 2.7 2.6 1.9

ns

A or B before LE↓, CLK low

2.6 2.0 2 1.3

A or B after CLK↑ 2 2.1 2 2.1

thHold time

A or B after LE↓

1.3 1.2 0.9 1.2

ns

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

SN54LVT16501 SN74LVT16501

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN MAX MIN MAX MIN TYP†MAX MIN MAX

f

max

150 125 150 125 MHz

t

PLH

1.7 5.4 6.8 1.7 3 5.4 6.8

t

PHL

B

or

A

A or B

1.6 6 7.8 1.6 3.2 5.9 7.7

ns

t

PLH

2.3 7.3 9 2.3 4 7 8.5

t

PHL

LEBA

or

LEAB

A or B

2.7 8.2 9.8 2.7 4.3 7.9 9.7

ns

t

PLH

CLKBA or

2.5 8.3 9.7 2.5 4.1 7.9 9.2

t

PHL

CLKAB

A or B

3.5 9.4 10.7 3.5 5.4 8.9 10.4

ns

t

PZH

1.2 5.1 6.1 1.2 3 5 5.9

t

PZL

OEBA

or

OEAB

A or B

1.5 5.9 7 1.5 3 5.8 6.9

ns

t

PHZ

2.7 7.5 8.5 2.7 4.6 7.4 8.3

t

PLZ

OEBA or OEAB

A or B

2.8 6.8 7.5 2.8 4.7 6.7 7.2

ns

†

All typical values are at VCC = 3.3 V, TA = 25°C.

SN54LVT16501, SN74LVT16501

3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS147G – MAY 1992 – REVISED NOVEMBER 1996

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

t

h

t

su

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

6 V

Open

GND

500 Ω

500 Ω

Data Input

Timing Input

1.5 V

2.7 V

0 V

1.5 V 1.5 V

2.7 V

0 V

2.7 V

0 V

1.5 V 1.5 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

1.5 V 1.5 V

2.7 V

0 V

1.5 V1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

1.5 V1.5 V

3 V

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

[

0 V

2.7 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

6 V

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

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Copyright  1998, Texas Instruments Incorporated