SN54LVT16500, SN74LVT16500
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS146D – MAY 1992 – REVISED NOVEMBER 1996
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
D
Members of the Texas Instruments
Widebus
D
Support Mixed-Mode Signal Operation (5-V
Family
Input and Output Voltages With 3.3-V VCC)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model
(C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Support Live Insertion
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes
PCB Layout
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
SN54LVT16500. . . WD PACKAGE
SN74LVT16500. . . DGG OR DL PACKAGE
OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
LEBA
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
GND
The ’L VT16500 are 18-bit universal bus transceivers designed for low-voltage (3.3-V) VCC operation, but with
the capability to provide a TTL interface to a 5-V system environment.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low , the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A-bus data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB
is active high. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are in
the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and UBT are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
SN54LVT16500, SN74LVT16500
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS146D – MAY 1992 – REVISED NOVEMBER 1996
description (continued)
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE
should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the
current-sourcing capability of the driver.
The SN74L VT16500 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages,
which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed
circuit board area.
The SN54L VT16500 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVT16500 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OEAB LEAB CLKAB A
L X X X Z
H HXLL
H HXHH
H L ↓ LL
H L ↓ HH
H LHXB
H L L X B
†
A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA
‡
Output level before the indicated steady-state input
conditions were established
§
Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was low before LEAB went low
, LEBA, and CLKBA.
†
OUTPUT
B
‡
0
§
0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT16500, SN74LVT16500
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS146D – MAY 1992 – REVISED NOVEMBER 1996
logic symbol
†
OEAB
CLKAB
LEAB
OEBA
CLKBA
LEBA
1
55
2
27
30
28
3
A1 B1
5
A2
6
A3
8
A4
9
A5
10
A6
12
A7
13
A8
14
A9
15
A10
16
A11
17
A12
19
A13
20
A14
21
A15
23
A16
24
A17
26
A18
EN1
C3
G2
EN4
C6
G5
3D
4
2C3
5C6
11
1
6D
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LVT16500, SN74LVT16500
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS146D – MAY 1992 – REVISED NOVEMBER 1996
logic diagram (positive logic)
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
CLK
1D
C1
1D
C1
CLK
54
B1
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state, V
Current into any output in the low state, IO: SN54LVT16500 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVT16500 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
(see Note 2): SN54LVT16500 48 mA. . . . . . . . . . . . . . . . . . . . . . .
O
SN74LVT16500 64 mA. . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Maximum power dissipation at T
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
= 55°C (in still air) (see Note 3):DGG package 1 W. . . . . . . . . . . . . . . . . . .
A
DL package 1.4 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Book
.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Package Thermal Considerations
application note in the
(see Note 1) –0.5 V to 7 V. . . .
O
ABT Advanced BiCMOS T echnology Data
†
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
SN54LVT16500, SN74LVT16500
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS146D – MAY 1992 – REVISED NOVEMBER 1996
recommended operating conditions (see Note 4)
SN54LVT16500 SN74LVT16500
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T
A
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 °C
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LVT16500, SN74LVT16500
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
3 V
V
V
V
V
V
V
‡
I
V
V
A or B ports
A
I
CC
mA
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS146D – MAY 1992 – REVISED NOVEMBER 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVT16500 SN74LVT16500
MIN TYP†MAX MIN TYP†MAX
V
IK
OH
OL
I
I
I
off
I(hold)
I
OZH
I
OZL
∆I
CC
C
i
C
io
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
Unused pins at VCC or GND
§
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = –8 mA 2.4 2.4
=
CC
= 2.7
CC
= 3
CC
VCC = 3.6 V, VI = VCC or GND
VCC = 0 or 3.6 V, VI = 5.5 V
VCC = 3.6 V
VCC = 0, VI or VO = 0 to 4.5 V ±100 ±100 µA
= 3
CC
VCC = 3.6 V, VO = 3 V 1 1 µA
VCC = 3.6 V, VO = 0.5 V –1 –1 µA
VCC = 3.6 V, IO = 0,
VI = VCC or GND
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
§
Other inputs at VCC or GND
VI = 3 V or 0 3.5 3.5 pF
VO = 3 V or 0 12 12 pF
IOH = –24 mA 2
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
IOL = 32 mA 0.5 0.5
IOL = 48 mA 0.55
IOL = 64 mA 0.55
Control
inputs
VI = 5.5 V
VI = V
CC
VI = 0 –10 –10
VI = 0.8 V
VI = 2 V
A or B ports
p
Outputs high 0.12 0.12
Outputs low
Outputs
disabled
75 75
–75 –75
±1 ±1
10 10
20 20
5 5
5 5
0.12 0.12
0.2 0.2 mA
µA
µ
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
twPulse duration
ns
tsuSet
thHold time
ns
B
A
A or B
ns
LEBA
LEAB
A or B
ns
A or B
ns
A or B
ns
A or B
ns
SN54LVT16500, SN74LVT16500
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS146D – MAY 1992 – REVISED NOVEMBER 1996
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVT16500 SN74LVT16500
f
clock
VCC = 3.3 V
± 0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
Clock frequency 0 150 0 125 0 150 0 125 MHz
LE high 3.3 3.3 3.3 3.3
CLK high or low 3.3 3.3 3.3 3.3
A before CLKAB↓ 1.8 1.1 1.8 1.1
up time
B before CLKBA↓ 1.9 1.2 1.9 1.2
A or B before LE↓ , CLK high
A or B before LE↓ , CLK low
A or B after CLK↓ 1.2 1.2 1.2 1.2
A or B after LE↓
2.2 1.3 2.2 1.3
2.7 1.9 2.7 1.9
0.9 1.1 0.9 1.1
VCC = 2.7 V
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVT16500 SN74LVT16500
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
†
PLZ
All typical values are at VCC = 3.3 V, TA = 25°C.
FROM
(INPUT)
or
or
CLKBA or
CLKAB
OEBA or
OEAB
OEBA or
OEAB
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
150 125 150 125 MHz
1.7 5.8 7 1.7 3 5.4 6.8
1.6 6 7.8 1.6 3.2 5.9 7.7
2.3 7.3 8.9 2.3 4 7 8.5
2.7 8.2 9.8 2.7 4.3 7.9 9.7
2 7.4 8.8 2 4.1 7 8.3
2.4 8.1 10 2.4 4.4 7.9 9.9
1.2 5.2 6.1 1.2 3 5 5.9
1.5 5.9 7 1.5 3 5.8 6.9
2.7 7.7 8.6 2.7 4.6 7.4 8.3
2.8 7.3 7.7 2.8 4.7 6.7 7.2
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
VCC = 2.7 V
UNIT
ns
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54LVT16500, SN74LVT16500
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS146D – MAY 1992 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
t
w
1.5 V
500 Ω
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Output
Output
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
Input
t
PLH
t
PHL
INVERTING AND NONINVERTING OUTPUTS
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
1.5 V
t
1.5 V1.5 V
S1
PHL
PLH
2.7 V
0 V
V
OH
V
OL
V
OH
V
OL
6 V
Open
GND
2.7 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
1.5 V
Open
6 V
GND
t
h
1.5 V
VOL + 0.3 V
VOH – 0.3 V
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
t
PZL
t
PLZ
1.5 V
t
t
PZH
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
VOLTAGE WAVEFORMS
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
[
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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